AD9213 datasheet(31/110 Pages) AD

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Data Sheet

AD9213

Rev. A | Page 31 of 110

Input Overvoltage Clamp

The AD9213 has an on-chip overvoltage clamp placed differ-

entially across the ADC analog inputs to protect the input

buffer of the device from large voltage excursions, as shown in

Figure 89. During an overvoltage event, this N-type metal-oxide

semiconductor (NMOS) clamp effectively shorts the on-chip,

50 Ω, differential input termination, attenuating the input level.

The clamping circuit detects differential overvoltage, but does

not sense the input VCM. The clamp attenuation is at its

maximum at fIN < 250 MHz. When the fIN > 250 MHz, clamp

circuit attenuation levels are lower. Higher input frequencies

result in a higher clamp threshold and a higher clamped input

level.

Adding board-level circuitry to protect the ADC inputs from

periodic, large voltage excursions often compromises system

performance. This built in clamp allows increased typical input

voltage levels and improved system performance.

During an overvoltage event, the active clamp circuit reduces

the on-chip, ADC input 50 Ω differential termination (load

termination resistance seen by the ADC signal source).

This reduction can cause reflections back to the circuitry that

drives the ADC. Ensure that the driving circuitry is not damaged

by potential large signals created with these reflections.

The user must ensure system reliability at their system specific

conditions.

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the

AD9213. This internal 0.5 V reference is used to set the full-

scale input range of the ADC.

The user has the option of applying a reference voltage from an

external source to the VREF pin. See Figure 75 for guidance

regarding appropriate external references a given application.

To enable the option to apply a reference voltage from an

external source, make the following writes: Register 0x1615 =

0x01, enable VREF import path, and Register 0x1616 = 0x01,

enable VREF import circuit.

These registers must be written immediately prior to Step 5

described in the Startup Sequence section.

CLAMP

INPUT

SOURCE

25Ω

50Ω

25Ω

Figure 89. Input Overvoltage Clamp

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