AD9213 datasheet(30/110 Pages) AD

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AD9213

Data Sheet

Rev. A | Page 30 of 110

THEORY OF OPERATION

The AD9213 is a single ADC with 16 JESD204B output lane

pairs. The ADC is designed to sample wide bandwidth analog

signals of up to 6.5 GHz. The AD9213 is optimized for wide input

bandwidth, high sampling rate, excellent linearity, and low

power in a small package.

The ADC core features a multistage, differential pipelined

architecture with integrated output error correction logic. The

AD9213 analog input features wide input bandwidth that

supports a variety of input ranges. An integrated voltage

reference eases design considerations.

A programmable threshold detector allows monitoring of the

signal power in the digital backend of the ADC. If the signal

level exceeds the programmable threshold, the FD indicator

goes high. Because this threshold indicator has low latency, the

user can quickly turn down the system gain to avoid an

overrange condition at the ADC input.

The Subclass 1 JESD204B-based high speed serialized output data

lanes can be configured to multiple configurations, depending

on the sample rate and the decimation ratio. Multiple device

synchronization is supported through the SYSREF_x and

SYNCINB_x input pins.

ADC ARCHITECTURE

The architecture of the AD9213 consists of an input buffered,

pipelined ADC. The input buffer is designed to provide a

termination impedance to the analog input signal of 50 Ω. The

equivalent circuit diagram of the analog input termination is

shown in Figure 77. The input buffer is optimized for high

linearity, low noise, and low power.

The quantized outputs from each stage are combined into a

final 12-bit result in the digital correction logic. The pipelined

architecture permits the first stage to operate with a new input

sample. Simultaneously, the remaining stages operate with the

preceding samples. Sampling occurs on the rising edge of the clock.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9213 is a differential buffer. The

internal common-mode voltage of the buffer is AVDD/2

(nominally 0.5 V). The clock signal alternately switches the

input circuit between sample mode and hold mode.

At radio frequencies, care must be taken when designing the

network between the signal source and the AD9213 inputs.

Additional loading affects bandwidth and possibly signal

integrity. For more information, refer to the Analog Dialogue

article Transformer-Coupled Front-End for Wideband A/D

Converters (Volume 39, April 2005). In general, the specific

configuration and component values depend on the application.

For best dynamic performance, the source impedances driving

VIN_P and VIN_N must be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC. An internal reference

buffer creates a differential reference that defines the span of the

ADC core.

Differential Input Configurations

There are several ways to drive the AD9213, either actively or

passively. However, optimal performance is achieved by driving

the analog input differentially.

For applications where SNR and SFDR are key parameters,

differential transformer coupling is the recommended input

configuration, because the noise performance of most amplifiers

is not adequate to achieve the true performance of the AD9213.

For low to midrange frequencies, a double balun or double trans-

former network is recommended for optimal performance of

the AD9213. For higher frequencies, remove some of the front-

end passive components to ensure wideband operation.

Input Common Mode

The analog inputs of the AD9213 are internally biased to the

common mode (0.50 V) by default.

In dc-coupled applications, the VCM of the signal source must be

biased to 0.50 V to ensure proper ADC operation. For these

applications, the internal biasing of the input buffer must be

disabled, and the dc offset nulling must also be disabled.

The following is pseudo code for the register writes to configure

the input buffer for dc coupling.

For dc coupling, without using the VCM output pin, make the

following writes: Register 0x1617 = 0x01, dc coupling mode,

nulling disabled, and Register 0x151A = 0x00, internal biasing

disabled, VCM output disabled.

For DC coupling, with the VCM output pin enabled, make the

following writes: Register 0x1617 = 0x01, dc coupling mode,

nulling disabled, and Register 0x151A = 0x02, internal biasing

disabled, VCM output enabled (for providing VCM level to a

driver amplifier).

The VCM output can be used to set the VCM of an amplifier

driving AD9213. The VCM output buffer has a series output

resistance of 100 Ω. A load on the VCM pin reduces the output

voltage, which must be accounted for when loading the VCM

output. The VCM output is not intended to drive high fanout,

multiple load applications.

See Figure 22 and Figure 54 for information regarding variation

in typical performance with respect to the VCM.

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