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AD9213 Datasheet(PDF) 63 Page - Analog Devices

Part # AD9213
Description  12-Bit, 6 GSPS/10.25 GSPS, JESD204B, RF Analog-to-Digital Converter
PDF  110 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9213 Datasheet(HTML) 63 Page - Analog Devices

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Data Sheet
AD9213
Rev. A | Page 63 of 110
LATENCY
END TO END TOTAL LATENCY
Total latency in the AD9213 is dependent on the chip application
mode and the JESD204B configuration. For any given combination
of these parameters, the latency is deterministic, however, the
value of this deterministic latency must be calculated as
described in the Example Latency Calculations section.
Table 28 shows the combined latency through the ADC and
DSP for the different chip application modes supported by the
AD9213. Table 29 shows the latency through the JESD204B
block for each application mode based on the M/L ratio. For
both tables, latency is typical and is in units of the encode clock.
The latency through the JESD204B block does not depend on
the output data type (real or complex). Therefore, data type is
not included in Table 28 and Table 29.
To determine the total latency, select the appropriate ADC + DSP
latency from Table 28 and add it to the appropriate JESD204B
latency from Table 29.
EXAMPLE LATENCY CALCULATIONS
An example configuration with latency calculation is shown
below:
•
ADC application mode = full bandwidth
•
Real outputs
•
L = 16, M = 1, F = 1, S = 8 (JESD204B mode)
•
M/L = 0.0625
•
Latency = 187 encode clock periods + 180 encode clock
periods = 367 encode clock periods
LMFC REFERENCED LATENCY
Some FPGA vendors may require the end user to know LMFC
referenced latency to make appropriate deterministic latency
adjustments. If they are required, the latency values in Table 28
and Table 29 can be used for the analog input to LMFC and
LMFC to data output latency values, respectively.
Table 28. Typical Latency Through the ADC + DSP Blocks (Number of Sample Clocks)1
Chip Application Mode
Enabled Filters
ADC + DSP Latency (Clock Cycles)
Full Bandwidth
Not applicable
180
DCM1, Real
HB1
520
DCM2
Complex
HB1
518
Real
HB2 + HB1
866
DCM3, Real
TB2 + HB1
1273
DCM4
Complex
HB2 + HB1
894
Real
HB3 +HB2 + HB1
1655
DCM6
Complex
TB2 + HB1
1282
Real
TB2 + HB2 + HB1
2339
DCM8
Complex
HB3 +HB2 + HB1
1662
Real
HB4 + HB3 + HB2 + HB1
3200
DCM12
Complex
TB2 + HB2 + HB1
2428
Real
TB2 + HB3 + HB2 + HB1
4540
DCM16
Complex
HB4 + HB3 + HB2 + HB1
3201
Real
HB5 + HB4 + HB3 + HB2 + HB1
6268
DCM24
Complex
TB2 + HB3 + HB2 + HB1
4733
Real
TB2 + HB4 + HB3 + HB2 + HB1
8582
DCM32
Complex
HB5 + HB4 + HB3 + HB2 + HB1
6273
Real
HB6 + HB5 + HB4 + HB3 + HB2 + HB1
12,415
DCM48
Complex
TB2 + HB4 + HB3 + HB2 + HB1
9337
Real
TB2 + HB5 + HB4 + HB3 + HB2 + HB1
17030



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