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AD9213 Datasheet(PDF) 64 Page - Analog Devices |
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AD9213 Datasheet(HTML) 64 Page - Analog Devices |
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64 / 110 page ![]() AD9213 Data Sheet Rev. A | Page 64 of 110 Chip Application Mode Enabled Filters ADC + DSP Latency (Clock Cycles) DCM64 Complex HB6 + HB5 + HB4 + HB3 + HB2 + HB1 12416 Real HB7 + HB6 + HB5 + HB4 + HB3 + HB2 + HB1 24707 DCM96, Complex TB2 + HB5 + HB4 + HB3 + HB2 + HB1 18552 DCM128, Complex HB7 + HB6 + HB5 + HB4 + HB3 + HB2 + HB1 24705 1 DCMx indicates the decimation ratio. Table 29. Typical Latency Through JESD204B Block (Number of Sample Clocks)1,2 Chip Application Mode M/L Ratio3 0.0625 0.125 0.25 0.5 1 2 4 8 Full Bandwidth 187 108 59 N/A N/A N/A N/A N/A DCM1, Real 195 112 N/A N/A N/A N/A N/A DCM2 Complex N/A 236 140 N/A N/A N/A N/A N/A Real 396 236 136 N/A N/A N/A N/A N/A DCM3, Real 606 347 197 N/A N/A N/A N/A N/A DCM4 Complex N/A 478 280 150 N/A N/A N/A N/A Real 810 467 265 130 N/A N/A N/A N/A DCM6 Complex N/A 738 436 246 N/A N/A N/A N/A Real 1011 N/A N/A N/A N/A N/A N/A N/A DCM8 Complex N/A 830 574 313 182 N/A N/A N/A Real 1281 893 330 190 N/A N/A N/A DCM12 Complex N/A N/A 852 N/A N/A N/A N/A N/A Real N/A 1264 877 N/A 248 N/A N/A N/A DCM16 Complex N/A N/A 1054 689 424 N/A N/A N/A Real 2437 N/A N/A 614 334 N/A N/A N/A DCM24 Complex N/A 2212 N/A N/A 516 313 N/A N/A Real N/A 2302 1577 1132 725 N/A N/A N/A DCM32 Complex N/A 3073 N/A N/A 850 576 N/A N/A Real N/A 3198 N/A N/A 803 N/A N/A N/A DCM48 Complex N/A N/A N/A 1457 773 N/A N/A N/A Real N/A N/A N/A 2066 1361 N/A N/A N/A DCM64 Complex N/A N/A 3988 2306 1685 1123 N/A N/A Real N/A N/A N/A 2499 1697 N/A N/A N/A DCM96, Complex N/A N/A 5013 2630 1400 798 N/A N/A DCM128, Complex N/A N/A N/A 4484 2949 2115 N/A N/A 1 N/A means not applicable and indicates that the application mode is not supported at the M/L ratio listed. 2 High density (HD) bit is set to zero (HD = 0) for all the numbers listed in this table. 3 M/L ratio is the number of converters divided by the number of lanes for the configuration. |
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