AD9213 datasheet(78/110 Pages) AD

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AD9213

Data Sheet

Rev. A | Page 78 of 110

Address

Bits

Bit Name

Settings

Description

Default

Access

JTX_SYNC_PIN_TYPE

JESD204B Serial SYNCINB_x Logic Type.

0x1

R/W

0 SYNCINB_x pin type. CMOS, single-ended

SYNCINB_x input. SYNCINB_P used.

Requires user to set Register 0x508, Bit 5.

1 SYNCINB_x pin type. LVDS differential pair

SYNCINB_x input. Requires 100 Ω, external

differential termination.

Reserved

Reserved.

0x0

JTX_8B10B_BYPASS

JESD204B Serial 8-Bit/10-Bit Bypass (Test

Mode Only).

0x0

R/W

0 8-bit/10-bit enabled.

1 8-bit/10-bit bypassed (two most significant

bits are 0).

JTX_10B_INV

JESD204B 10b Serial Transmit Bit Invert.

0x0

R/W

0Normal.

1 Invert a, b, c, d, e, f, g, h, i, and j symbols.

JTX_10B_MIRROR

JESD204B 10-Bit Serial Transmit Bit Mirror.

0x0

R/W

0x505

JTX_LINK_CTRL3

[7:6]

JTX_CHKSUM_MODE

JESD204B Checksum Mode.

0x0

R/W

00 Checksum is the sum of all 8-bit registers in

the link configuration table.

01 Checksum is the sum of all individual link

configuration fields (LSB aligned).

10 Checksum is disabled (set to zero). For test

purposes only.

11 Unused.

[5:4]

JTX_TEST_GEN_SEL

JESD204B Serial Test Generation Input

Selection.

0x0

R/W

00 N' sample input.

01 10-bit data at 8-bit/10-bit output (for PHY

testing).

10 8-bit data at scrambler input.

[3:0]

JTX_TEST_GEN_MODE

JESD204B Serial Test Generation Mode.

0x0

R/W

0000 Normal operation (test mode disabled).

0001 Alternating checker board.

0010 1/0 word toggle.

0011 31-bit PN sequence: x31 + x28 + 1.

0100 23-bit PN sequence: x23 + x18 + 1.

0101 15-bit PN sequence: x15 + x14 + 1.

0110 9-bit PN sequence: x9 + x5 + 1.

0111 7-bit sequence: x7 + x6 + 1.

1000 Ramp output.

1110 Continuous/repeat user test.

1111 Single use test.

0x506

JTX_LINK_CTRL4

[7:4]

JTX_ILAS_DELAY

Initial Lane Alignment Delay.

0x0

R/W

0000 Transmit ILAS on first LMFC after SYNCINB_x

is deasserted.

0001 Transmit ILAS on second LMFC after

SYNCINB_x is deasserted.

0010 Transmit ILAS on third LMFC after

SYNCINB_x is deasserted.

0011 Transmit ILAS on fourth LMFC after

SYNCINB_x is deasserted.

0100 Transmit ILAS on fifth LMFC after

SYNCINB_x is deasserted.

0101 Transmit ILAS on sixth LMFC after

SYNCINB_x is deasserted.

0110 Transmit ILAS on seven LMFC after

SYNCINB_x is deasserted.

0111 Transmit ILAS on eighth LMFC after

SYNCINB_x is deasserted.

1000 Transmit ILAS on ninth LMFC after

SYNCINB_x is deasserted.

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