AD9213 datasheet(69/110 Pages) AD

69 / 110 page

Data Sheet

AD9213

Rev. A | Page 69 of 110

7. Set to lock once mode. When Register 0x1622, Bits[1:0] =

0x0, the MCS does nothing. When Register 0x1622,

Bits[1:0] = 0x2, the MCS locks when it has successfully

acquired the averaged SYSREF signal, and remain locked,

even if timing conditions change due to temperature. The

MCS does not relock in response to changed timing

conditions.

8. Set SYSREF_RESYNC. Write Register 0x693 = SYSREF_

RESYNC = 0x01. Always set this register to 0x01 for any

Subclass 1 operation.

9. Set the USER_CTRL_TRANSFER bit (Register 0x1600,

Bit 0 = 1). When set to 1, this bit applies the latest MCS

settings. Perform this write every time any of the registers

described in this section are changed. This bit is self

clearing.

10. Check for SYSREF_x lock in averaging mode after a wait.

After the wait interval, check MCS lock by reading

averaging count × SYSREF_x period ×100. For example, if

the fSYSREF_x = 4.8828125 MHz, the approximate SYSREF_x

period is 205 ns. For an averaging count is 16,000, the wait

interval is 1000 × 16 × 205 ns × 100 = 328 ms.

If all AD9213 devices intended to be synchronized show MCS

lock, the desired result is achieved. Each device has a local

SYSREF from which to align the LMFC, which in turn results in

deterministic latency. Given enough time, it is highly unlikely

that MCS lock is not achieved in lock once mode.

If one or more AD9213s do not achieve MCS lock within the

allotted time, the following steps can be taken for all AD9213s

to achieve MCS lock:

1. More time can be allotted to achieve MCS lock. In the

devices not achieving MCS lock quickly, local SYSREF is by

random chance closely aligned with, and slightly ahead of,

the applied SYSREF signal, causing a delay in the MCS lock

process. This state of the local SYSREF and the applied

SYSREF_x being closely aligned is the desired result.

However, until the MCS Lock bit goes high, the local

SYSREF is not sent to downstream digital circuitry. Longer

time taken to achieve MCS lock is not indicative of reduced

time alignment accuracy of the local SYSREF.

2. Alternatively, delay can be added to the SYSREF_x path

within AD9213 to delay the internal waveform used by the

MCS block to create the local SYSREF.

a. On the devices that have not achieved MCS lock,

enable the fine delay cell by setting Register 0x1516,

Bit 0 = 1.

b. Add approximately half of a sample clock cycle delay.

Each LSB of Register 0x1517 represents ~1.1 ps delay.

For example, half of a 10 GHz clock period is 50 ps.

Therefore, set Register 0x1517, Bits[7:0] = 0x2D (45 ×

1.1 ps steps = 49.5 ps).

c. Toggle the transfer bit. Register 0x1600, Bit 0 = 1 to

restart the SYSREF_x averaging and MCS lock

procedure.

d. Check for MCS lock, Register 0x151E, Bit 1 = 1.

3. If MCS lock is still not achieved, there are other issues with

the setup. Check that the frequency of SYSREF complies

with the requirements stated before Step 1. The signal

sources of the sample clock and SYSREF must be phase

locked. The time difference between the externally applied

SYSREF_x signal and the averaged internal version can be

monitored by reading the contents of Register 0x1623,

These are four 8-bit registers that comprise a 32-bit word

(CALC_TIME_DIFF[31:0]) signifying the calculated time

difference between the input SYSREF_x signal and the

averaged local SYSREF. Register 0x1623 contains the LSBs

and Register 0x1626 contains the MSBs. The TDC is

connected to the SYSREF_x input, and the local SYSREF

counter. This number is an average of TDC measurements

as determined by Register 0x162A and Register 0x162B.

When MCS lock is achieved, the time difference between the

externally applied SYSREF signal and the averaged internal

version is <1 ADC clock period.

AD9213 Datasheet(PDF) 69 Page - Analog Devices

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