AD9213 datasheet(74/110 Pages) AD

74 / 110 page

AD9213

Data Sheet

Rev. A | Page 74 of 110

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLES

Table 36 documents the default hexadecimal value for each

hexadecimal address shown. All address locations that are not

included in Table 36 are not currently supported for this device

and should not be written.

Open and Reserved Locations

All address and bit locations that are not included in Table 36

are not currently supported for this device. Write unused bits of

a valid address location with 0s unless the default value is set

otherwise. Writing to these locations is required only when part

of an address location is unassigned. If the entire address location is

open, do not write to this address location.

Default Values

After the AD9213 is reset, critical registers are loaded with

default values. The default values for the registers are given in

Table 36.

Logic Levels

An explanation of logic level terminology follows:



Bit is set is synonymous with bit is set to Logic 1 or writing

Logic 1 for the bit.



Clear a bit is synonymous with bit is set to Logic 0 or

writing Logic 0 for the bit.



X denotes a don’t care bit.

SPI Soft Reset

After issuing a soft reset by programming Register 0x000, the

AD9213 requires 300 ms to recover. When programming the

AD9213 for application setup, ensure that an adequate delay is

programmed into the firmware after asserting the soft reset and

before starting the device setup.

Table 36. Register Map

Address

Bits

Bit Name

Settings

Description

Default

Access

0x0

SPI_CONFIG_A

SOFT_RESET_1

Initiates a Reset Equivalent to a Hard Reset.

0x0

R/W

0Do nothing.

1 Reset the SPI and registers (self clearing).

LSB_FIRST_1

LSB/MSB Bit Shift First.

0x0

R/W

0 Most significant bit shifted first.

1 Least significant bit shifted first.

ADDR_ASCENSION_1

Multibyte SPI Operations Address

Increment.

0x1

R/W

0Autodecrement.

1 Autoincrement.

[4:3]

Reserved

Reserved.

0x0

ADDR_ASCENSION_0

Multibyte SPI Operations Address

Increment.

0x1

R/W

0Autodecrement.

1 Autoincrement.

LSB_FIRST_0

LSB/MSB Bit Shift First.

0x0

R/W

0 Most significant bit shifted first.

1 Least significant bit shifted first.

SOFT_RESET_0

Initiates a Reset Equivalent to a Hard Reset.

0x0

R/W

0Do nothing.

1 Reset the SPI and registers (self clearing).

0x2

DEVICE_CONFIG

[7:2]

Reserved

Reserved.

0x3C

[1:0]

OP_MODE

Operating Mode.

0x0

R/W

00 Normal operation.

10 Standby mode.

11 Power-down mode.

0x3

CHIP_TYPE

[7:0]

CHIP_TYPE

High Speed ADCs.

0x3

0x4

CHIP_ID_LSB

[7:0]

CHIP_ID[7:0]

Chip ID.

0xE5

0x5

CHIP_ID_MSB

[7:0]

CHIP_ID[15:8]

Chip ID.

0x0

0xA

CHIP_SCRATCH

[7:0]

CHIP_SCRATCH

Chip Scratch Pad Register.

0x0

R/W

0xC

VENDOR_ID_LSB

[7:0]

CHIP_VENDOR_ID[7:0]

Vendor ID.

0x56

0xD

VENDOR_ID_MSB

[7:0]

CHIP_VENDOR_

ID[15:8]

Vendor ID.

0x4

0x26

GEN_CTRL

[7:4]

Reserved

Reserved.

0x0

CLK_SWITCH

Clock Ready (Self Clearing).

0x0

R/W

[2:0]

Reserved

Reserved.

0x0

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