AD9213 datasheet(60/110 Pages) AD

60 / 110 page

AD9213

Data Sheet

Rev. A | Page 60 of 110

SETTING UP THE AD9213 DIGITAL INTERFACE

The AD9213 has one JESD204B link. The device offers an easy

way to set up the JESD204B link through the JESD204B quick

configuration register (Register 0x502). The serial outputs

(SERDOUT0_x to SERDOUT15_x) are considered to be part of

one JESD204B link. The basic parameters that determine the

link setup are:

•

Number of lanes per link (L)

•

Number of converters per link (M)

•

Number of octets per frame (F)

If the internal DDC is used for on-chip digital processing, M

represents the number of virtual converters.

The maximum lane rate allowed by the AD9213 is 16 Gbps. The

lane line rate is related to the JESD204B parameters using the

following equation:

Rate

Line

Lane

OUT













where fOUT is the fADC_CLOCK divided by the decimation ratio.

The DCM is the parameter programmed in Register 0x631.

The following steps can be used to configure the output:

1. Power down the link.

2. Select JESD204B link configuration options.

3. Configure detailed options.

4. Set output lane mapping (optional).

5. Set additional driver configuration options (optional).

6. Power up the link.

If the lane line rate calculated is less than 6.8 Gbps, select

the low line rate option by programming a value of 0x01 to

Table 25, Table 26, and Table 27 show the JESD204B output

configurations supported for N΄ = 16, N΄ = 12 and N΄ = 8 for a

given number of virtual converters. Take care to ensure that the

serial line rate for a given configuration is within the supported

range of 1.7 Gbps to 16 Gbps.

JESD204B Transport Layer Settings

See the JESD204B Overview section for details regarding the

transport layer information listed in Table 25, Table 26, and

Table 27.

Serial Line Rates

In Table 25, Table 26, and Table 27, the serial line rates are as

follows:

•

fIN = ADC input sample rate

•

CDR = chip decimation ratio

•

FOUT = output sample rate = fIN/CDR.

•

SLR = JESD204B serial line rate

The following equations must be met due to internal clock

divider requirements:

•

SLR ≥ 1700 Mbps and SLR ≤ 16,000 Mbps.

•

SLR/40 ≤ fIN

•

20 × CDR × fOUT / SLR ≤ 512

•

When the SLR is ≤16,000 Mbps and >13,600 Mbps,

JTX_LOW_LINE_RATE, Register 0x500, Bits[3:0] must be

set to 0x3.

•

When the SLR is ≤13,600 Mbps and ≥6800 Mbps,

JTX_LOW_LINE_RATE, Register 0x500, Bits[3:0] must be

set to 0x0.

•

When the SLR is <6800 Mbps and ≥3400 Mbps,

JTX_LOW_LINE_RATE, Register 0x500, Bits[3:0]must be

set to 0x1.

•

When the SLR is <3400 Mbps and ≥1700 Mbps,

JTX_LOW_LINE_RATE, Register 0x500, Bits[3:0]must be

set to 0x5.

K Settings

In Table 25, Table 26, and Table 27, the number of samples per

converter per frame cycle, S, is calculated as follows:

•

S = 8 × F × L/(N' × M)

•

K = 32 is supported for all S

•

K = 16, 32 is supported for configurations except when

S = 1 and Register 0x630, Bit 4 = 1 in which case, only K =

32 is supported.

AD9213 Datasheet(PDF) 60 Page - Analog Devices

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