AD9213 datasheet(68/110 Pages) AD

68 / 110 page

AD9213

Data Sheet

Rev. A | Page 68 of 110

MCS AVERAGED SYSREF MODE SETUP

The following are the SYSREF_x signal constraints for MCS

averaged SYSREF mode:

•

(fCLK ÷ 8) ÷ (fSYSREF_x) must be a positive integer.

•

fSYSREF_x must be ≤ 500 MHz

•

The number of LMFC cycles (K) per SYSREF_x cycle must

be a positive integer.

To calculate LMFC frequency (fLMFC), use the following

conditions:

fLMFC = fS/(DCM × K × S)

S = 8 × F × L/(N’ × M)

K = 32 or 16 frames/multiframe

To configure the AD9213 for MCS averaged SYSREF_x mode,

take the followings steps:

1. Write Register 0x525, Bit 5 = 1 to select JESD204B Subclass 1

mode. Set the SYSREF_x period. All three of the following

registers must be written for the 24-bit KNOWN_SYSREF_

PERIOD word (KNOWN_SYSREF_PERIOD[23:0] =

(fCLK/8)/fSYSREF_x):

KNOWN_SYSREF_PERIOD[7:0]

b. Register 0x1628, Bits[7:0] =

KNOWN_SYSREF_PERIOD[15:8]

c. Register 0x1629, Bits[7:0] =

KNOWN_SYSREF_PERIOD[23:16]

For example, if fCLK = 10 GHz (chosen by user), then,

S = 8 × F × L/(N’ × M) = (8 × 2 × 16)/(16 × 1) = 16

(calculated automatically within AD9213)

fLFMC = fCLK/(DCM × K × S) = 10 × 10−9/(1 × 32 × 16) =

19,531,250 Hz

fSYSREF_x = 4.8828125 MHz, which is chosen for this example

to comply with the fLFMC and fSYSREF_x constraint.

With fSYSREF_x in compliance, KNOWN_SYSREF_PERIOD[23:0]

can be calculated:

KNOWN_SYSREF_PERIOD[23:0] =

10 10

256 0x100

4.8828125 10

CLK

SYSREF x

The following write operations must be made to set

KNOWN_SYSREF_PERIOD[23:0] = 0x100:

•

2. Set the sample clock period (Register 0x162D to

values in picoseconds and Bits[15:0] represent fractions of

picoseconds.

For example, if fCLK = 6 GHz (chosen by user), then,

Clock period = 1/6 GHz = 166.667 ps

166.66710 = A6.AAC016.

The following writes must be made to set

SAMPLE_CLOCK_PERIOD[31:0] = A6.AAC016:

•

3. Set the number of SYSREF_x pulses to ignore

(Register 0x1521, MCS_SYSREF_IGNORE_COUNT[7:0]).

Note that this value is system dependent on the number of

cycles required to stabilize the SYSREF_x signal. For

example, to ignore 100 SYSREF_x pulses, perform the

following write operation: Register 0x1521 Bits[7:0] =

MCS_SYSREF_IGNORE_COUNT[7:0] = 0x64.

4. Set the SYSREF_x averaging count (Register 0x162A,

Bits[7:0] and Register 0x162B, Bits[7:0]). The averaging

count is the number of SYSREF_x pulses the MCS uses to

determine the timing of the externally applied SYSREF_x

signal. The larger the averaging count, the more accurate

the result, but it takes longer to achieve MCS lock. Note

that the number of SYSREF_x pulses averaged is the

(Register contents + 1) × 16. The recommended value for

the register contents is ≥1000. For example, to set the

averaging count register contents = 1000 = 0x03E8,

perform the following write operations: Register 0x162A

Bits[7:0] = MCS_SYSREF_AVGING_COUNT[7:0] = 0xE8,

and Register 0x162B Bits[7:0] = MCS_SYSREF_

AVGING_COUNT[15:8] = 0x03. This example write

operation corresponds to averaging (1000 + 1) × 16 ≈

16,000 SYSREF_x pulses averaged.

5. Select MCS SYSREF averaging mode (Register 0x1621,

Bits[3:0]). This action selects averaging mode, which

averages the signal present on the analog input of the time

to digital converter (TDC) within the MCS block. The instan-

taneous period is calculated, and this is then averaged to

create a clean and stable internal SYSREF_x signal, available

for alignment of the LMFC. The following write operation

selects SYSREF averaging mode: Register 0x1621,

Bits[3:0] = 0x9.

6. Set the MCS phase slip mode (Register 0x1636, Bit 0 = 1).

Always set this bit to 1 for SYSREF_x averaging mode.

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