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AD9213 Datasheet(PDF) 77 Page - Analog Devices |
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AD9213 Datasheet(HTML) 77 Page - Analog Devices |
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77 / 110 page  Data Sheet AD9213 Rev. A | Page 77 of 110 Address Register Name Bits Bit Name Settings Description Default Access 0x501 PLL_STATUS 7 JTX_PLL_LOCKED PLL Locked Status Bit 0x1 R 0Not Locked. 1 Locked. [6:0] Reserved Reserved. 0x0 R 0x503 JTX_LINK_CTRL1 7 JTX_LINK_STDBY_MODE JESD204B Standby Mode. 0x0 R/W 0 Standby mode forces zeros for all converter samples. 1 Standby mode forces code group synchronization, /K28.5/characters. 6 JTX_TAIL_PN_EN JESD204B Serial Tail Bit Pseudo Random Number (PN) Enable. 0x0 R/W 0Disable. 1Enable. 5 JTX_TEST_SAMPLE_EN JESD204B Serial Test Sample Enable. 0x0 R/W 0 JESD204B test samples disabled. 1 JESD204B test samples enabled. Long transport layer test sample sequence sent on all link lanes (as specified in JESD204B Section 5.1.6.3). 4 JTX_LSYNC_EN JESD204B Serial Lane Synchronization Enable. 0x1 R/W 0 Disable FACI uses /K28.7/. 1 Enable FACI uses /K28.3/ and /K28.7/. [3:2] JTX_ILAS_MODE JESD204B Serial Initial Lane Alignment Sequence Mode. 0x1 R/W 0 Initial lane alignment sequence disabled (JESD204B Section 5.3.3.5). 1 Initial lane alignment sequence enabled (JESD204B Section 5.3.3.5). 11 Initial lane alignment sequence always in test mode. JESD204B data link layer test mode sent on all lanes where lane alignment sequence repeats as specified in JESD204B Section 5.3.3.8.s. 1 JTX_FACI_DISABLE JESD204B Serial Frame Alignment Character Insertion (FACI) Disable. 0x0 R/W 0 Frame alignment character insertion enabled (JESD204B Section 5.3.3.4). 1 Frame alignment character insertion disabled. For debug only (JESD204B Section 5.3.3.4). 0 JTX_LINK_PD JESD204B Serial Transmit Link Power Down (Active High). 0x0 R/W 0 JESD204B serial transmit link enabled. Transmission of the /K28.5/ characters for code group synchronization is controlled by the SYNCINB_x pins. 1 JESD204B serial transmit link powered down (held in reset and clock gated). 0x504 JTX_LINK_CTRL2 [7:6] JTX_SYNC_PIN_MODE JESD204B Serial Synchronization Mode. 0x0 R/W 0 Normal mode. 10 Ignore SYNCINB_x (force CGS). 11 Ignore SYNCINB_x (force ILAS/user data). 5 JTX_SYNC_PIN_INV JESD204B Serial Synchronization Pin Invert. 0x0 R/W 0 SYNCINB_x pin invert. SYNCINB_x pin not inverted. 1 SYNCINB_x pin invert. SYNCINB_x pin inverted. |
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