AD9213 datasheet(75/110 Pages) AD

75 / 110 page

Data Sheet

AD9213

Rev. A | Page 75 of 110

Address

Bits

Bit Name

Settings

Description

Default

Access

0x100

FD_CTRL

[7:3]

Reserved

Reserved.

0x0

FD_FINE_EN

Enable Fast Detect on Corrected ADC Data.

0x0

R/W

0 Fast detect disabled.

1 Fast detect enabled.

FD_FORCE_VAL

Force Value for the Fast Detect. This bit field

value is forced on the FD pin when

FD_FORCE is high.

0x0

R/W

FD_FORCE

Force the Fast Detect Output Pin.

0x0

R/W

0 Normal operation of the FD pin.

1 Force a value on the FD pin (see Bit 1).

0x101

FD_UP_THRESH_LSB

[7:0]

FD_UP_THRESH[7:0]

Fast Detect Upper Threshold Unsigned

Number. 11-bit value for the fast detect

upper threshold. The fast detect goes high if

the analog input is above the upper

threshold value for one fS/16 clock cycle.

0x0

R/W

0x102

FD_UP_THRESH_MSB

[7:3]

Reserved

Reserved.

0x0

[2:0]

FD_UP_THRESH[10:8]

Fast Detect Upper Threshold Unsigned

Number. 11-bit value for the fast detect

upper threshold. The fast detect goes high if

the analog input is above the upper

threshold value for one fS/16 clock cycle.

0x0

R/W

0x103

FD_LOW_THRESH_LSB

[7:0]

FD_LOW_THRESH[7:0]

Fast Detect Lower Threshold Unsigned

Number. 11-bit value for the fast detect

lower threshold. The fast detect goes low if

the analog input is below the lower

threshold value for DWELL_THRESH time.

0x0

R/W

0x104

FD_LOW_THRESH_MSB

[7:3]

Reserved

Reserved.

0x0

[2:0]

FD_LOW_THRESH[10:8]

Fast Detect Lower Threshold Unsigned

Number. 11-bit value for the fast detect

lower threshold. The fast detect goes low if

the analog input is below the lower

threshold value for DWELL_THRESH time.

0x0

R/W

0x105

FD_DWELL_THRESH_

LSB

[7:0]

FD_DWELL_THRESH[7:0]

Fast Detect Dwell Time Counter Target. The

fast detect goes low if the analog input is

below the fast detect lower threshold value

for the FD_DWELL_THRESH time. This is a

16-bit counter. Value is in multiples of 16.

0x0

R/W

0x106

FD_DWELL_THRESH_

MSB

[7:0]

FD_DWELL_

THRESH[15:8]

Fast Detect Dwell Time Counter Target. The

fast detect goes low if the analog input is

below the fast detect lower threshold value

for the FD_DWELL_THRESH time. This is a

16-bit counter. Value is in multiples of 16.

0x0

R/W

0x120

SMON_STATUS_0

[7:0]

SMON_STATUS[7:0]

20-bit Signal Monitor Serial Data Output

Bits. Signal monitor data output status bits.

Bits[19:9] contain the peak magnitude value

obtained over the programmable

SMON_PERIOD.

0x0

0x121

SMON_STATUS_1

[7:0]

SMON_STATUS[15:8]

20-bit Signal Monitor Serial Data Output

Bits. Signal monitor data output status bits.

Bits[19:9] contain the peak magnitude value

obtained over the programmable

SMON_PERIOD.

0x0

0x122

SMON_STATUS_2

[7:0]

SMON_STATUS[19:16]

20-bit Signal Monitor Serial Data Output

Bits. Signal monitor data output status bits.

Bits[19:9] contain the peak magnitude value

obtained over the programmable

SMON_PERIOD.

0x0

0x123

SMON_STATUS_FCNT

[7:0]

SMON_STATUS_FCNT

Signal Monitor Frame Counter. Increments

whenever period counter expires. The

counter value can be read back from this bit

field whenever the SMON_STATUS_UPDATE

signal is pulled high.

0x0

0x124

SMON_PERIOD_0

[7:0]

SMON_PERIOD[7:0]

2-Bit Value, Sets Number of Clock Cycles

that Signal Monitor Performs Operation.

24-bit period value over which the signal

monitor performs the peak detection. The

bit value must be in multiples of 16.

0x0

R/W

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