AD9213 datasheet(42/110 Pages) AD

42 / 110 page

AD9213

Data Sheet

Rev. A | Page 42 of 110

Figure 97 shows an example use case for coherent mode utilizing

three NCO channels. In this example, NCO Channel 0 is actively

downconverting Bandwidth 0 (B0) when NCO Channel 1 and

NCO Channel 2 are in standby mode and tuned to Bandwidth 1

(B1) and Bandwidth 2 (B2).

The phase coherent NCO switching feature allows an infinite

number of frequency hops that are all phase coherent. The initial

phase of the NCO is established at Time t0 from SYSREF_x

synchronization or the signal.

Switching the NCO FTW does not affect the phase. Only one

FTW is required with this feature. However, the user can use all

16 channels to queue up the next hop.

After SYSREF_x synchronization at startup, all NCOs across

multiple chips are inherently synchronized.

Setting Up the Multichannel NCO Feature

The first step to configure the multichannel NCO is to program

the FTWs. The AD9213 memory map has a FTW index register

for the DDC. This index determines which NCO channel

receives the FTW from the register map.

The following sequence describes the method for programming

the FTWs:

Write the DDC profile (phase) update register (Register 0x633,

Bit 7) to select the DDC profile (phase) update mode. The

update mode can be continuous or require chip transfer.

Write the FTW index register (Register 0x633, Bits[3:0]).

Write the FTW with the desired value. The FTW register

addresses are 0x634, 0x635, 0x636, 0x637, 0x638, and

0x639. This value is applied to the NCO channel index

mentioned in Step 1.

Repeat Step 1 and Step 2 for other NCO channels.

After setting the FTWs, the user must select an active NCO

channel. This selection can be done through the SPI registers,

the external GPIO[x] pins, or a profile select timer.

The following sequence describes the method for selecting the

active NCO channel using the SPI:

Set the NCO channel selection mode in Register 0x632,

Bits[7:4] to 0x0 to enable SPI selection.

Choose the active NCO channel in Register 0x632, Bits[3:0].

The following sequence describes the method for selecting the

active NCO channel using GPIO[x] CMOS pins.

Set NCO channel selection mode in Register 0x632,

Bits[7:4] to a value between 0x1 and 0xB to enable

GPIO[x] pin selection.

Configure the GPIO[x] pins as NCO channel selection

inputs by writing to Register 0x1606.

NCO switching is done by externally controlling the

GPIO[x] CMOS pins.

The following sequence describes the method for selecting the

active NCO channel using the TRIG_x pins.

Set the NCO channel selection input in Register 0x602.

Configure the TRIG_x pin in edge control mode by writing

to Bits[3:2] in Register 0x151E.

NCO switching is achieved by externally controlling the

TRIG_x pins.

NCO Synchronization

Each NCO contains a separate PAW. The initial reset value of

each PAW is set to zero and increments every clock cycle. The

instantaneous phase of the NCO is calculated using the PAW,

FTW, MAW, MBW, and POW.

Two methods can be used to synchronize multiple PAWs within

the chip:



Using the SPI: use the DDC soft reset bit in the DDC

synchronization control register (Register 0x600, Bit 4) to

reset all the PAWs in the chip. This reset is accomplished

by setting the DDC soft reset bit high, and then setting this

bit low. Note that this method can only be used to synchronize

DDC channels within the same chip.



Using the SYSREF_x pins: When a SYSREF_x pin is enabled

in the SYSREF control registers, and the DDC synchro-

nization is enabled in the DDC synchronization control

SYSREF_x or any subsequent edges of SYSREF_x resets all

the PAWs in the chip. Note that this method can be used to

synchronize DDC channels within the same chip or DDC

channels within separate chips (see Table 10).

The synchronization mechanism using SYSREF_x and TRIG_x

signals is shown in Figure 98.

CLOCK

GENERATION

FPGA

SYSREF_x

CLOCK(S)

SYSREF_x

DEVICE CLOCK

SYSREF_x

TRIG_x

ADC DEVICE 0

ADC DEVICE 1

ADC DEVICE 2

ADC DEVICE 3

Figure 98. System Using TRIG_x and SYSREF_x for Synchronization

AD9213 Datasheet(PDF) 42 Page - Analog Devices

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