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AD9213 Datasheet(PDF) 44 Page - Analog Devices |
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AD9213 Datasheet(HTML) 44 Page - Analog Devices |
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44 / 110 page  AD9213 Data Sheet Rev. A | Page 44 of 110 TRIG_x SENT BY FPGA TRIG_x SIGNAL ARRIVES AT ADC INPUT PINS TRIG_x SIGNAL REGISTERED BY ADC SYSREF_x DEVICE CLOCK LMFCs DON’T CARE DON’T CARE NCOs NCO SYNCHRONIZED LMFC SYNCHRONIZED BOARD PROPAGATION DELAY INPUT DELAY CONFIGURE MASTER AND SLAVE DEVICES ENABLE TRIG_x TRIG_x SENT BY FPGA TRIG_x RECEIVED BY ADC SYSTEM SYNCHRONIZATION ACHIEVED SYSREF_x IGNORED LMFC = LOCAL MULTIFRAME CLOCK NCO = NUMERICALLY CONTROLLED OSCILLATOR Figure 99. NCO Multichip Synchronization at Startup (Using TRIG_x and SYSREF_x) HB7 FIR DCM = 2 Q I Q I Q I REAL INPUT HB6 FIR DCM = 2 HB5 FIR DCM = 2 HB4 FIR DCM = 2 HB3 FIR DCM = 2 HB1 FIR DCM = 2 HB2 FIR DCM = 2 TB2 FIR DCM = 3 HB7 FIR DCM = 2 HB6 FIR DCM = 2 HB5 FIR DCM = 2 HB4 FIR DCM = 2 HB3 FIR DCM = 2 HB1 FIR DCM = 2 HB2 FIR DCM = 2 TB2 FIR DCM = 3 Figure 100. DDC Decimation Filter Block Diagram DDC Mixer Description When not bypassed (Register 0x606, Bits[3:0] ≠ 0x00), the DDC mixer performs a similar operation to an analog quadrature mixer. The DDC performs the downconversion of the input signal using the NCO frequency as a local oscillator. The input of the DDC is a real signal which means that a real mixer operation (with two multipliers) is performed. DDC NCO, Mixer Loss, and SFDR When mixing a real input signal down to baseband, −6 dB of loss is introduced in the signal due to filtering of the negative image. An additional −0.05 dB of loss is introduced by the NCO. The total loss of a real input signal mixed down to baseband is −6.05 dB, and it is recommended that the user compensate for this loss by enabling the 6 dB of gain in the gain stage of the DDC to recenter the dynamic range of the signal within the full scale of the output bits (see the DDC Gain Stage section for more information). The worst case spurious signal from the NCO is >102 dBc SFDR for all output frequencies. DDC DECIMATION FILTERS After the frequency translation stage, there are multiple decimation filter stages used to reduce the output data rate. After the carrier of interest is tuned down to dc (carrier frequency = 0 Hz), these filters efficiently lower the sample rate and providing sufficient alias rejection from unwanted adjacent carriers around the bandwidth of interest. Figure 100 shows a simplified block diagram of the decimation filter stage, and Table 11 describes the filter characteristics of the different FIR filter blocks. Table 11 and Table 12 show the different filter configurations selectable by including different filters. In all cases, the DDC filtering stage provides 80% of the available output bandwidth, <±0.001 dB of pass-band ripple, and >100 dB of stop band alias rejection. |
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