AD9213 datasheet(59/110 Pages) AD

59 / 110 page

Data Sheet

AD9213

Rev. A | Page 59 of 110

PHYSICAL LAYER (DRIVER) OUTPUTS

Digital Outputs, Timing, and Controls

The AD9213 physical layer consists of drivers that are defined in

the JEDEC Standard JESD204B, July 2011. The differential digital

outputs are powered up by default. The drivers use a dynamic

100 Ω internal termination to reduce unwanted reflections.

Place a 100 Ω differential termination resistor at each receiver

input to result in a nominal 300 mV p-p swing at the receiver

(see Figure 118). Alternatively, single-ended 50 Ω termination

can be used. When single-ended termination is used, the

termination voltage is JVDD/2.

SERDOUT_P[x]

DRVDD

VRXCM

SERDOUT_N[x]

OUTPUT SWING = 300mV p-p

0.1µF

100Ω

50Ω

0.1µF

RECEIVER

VCM = VRXCM

100Ω

DIFFERENTIAL

TRACE PAIR

Figure 118. AC-Coupled Digital Output Termination Example

The AD9213 digital outputs can interface with custom ASICs

and FPGA receivers, providing superior switching performance

in noisy environments. Single point-to-point network topologies

are recommended with a single differential 100 Ω termination

resistor placed as close to the receiver inputs as possible.

If there is no far-end receiver termination, or if there is poor

differential trace routing, timing errors can result. To avoid such

timing errors, it is recommended that the trace length be less

than six inches, and that the differential output traces be close

together and of equal lengths.

Figure 119 shows examples of the digital output data eye, time

interval error (TIE) jitter histogram, and bathtub curve for one

AD9213 lane running at 16Gbps. The format of the output data

is twos complement by default. To change the output data format,

see the Memory Map section (Register 0x622).

De-emphasis

De-emphasis enables the receiver eye diagram mask to be met

in conditions where the interconnect insertion loss does not

meet the JESD204B specification. Use the de-emphasis feature

only when the receiver is unable to recover the clock due to

excessive insertion loss. Under normal conditions, it is disabled

to conserve power. Additionally, enabling and setting too high a

de-emphasis value on a short link can cause the receiver eye

diagram to fail. Use the de-emphasis setting with caution

because it can increase electromagnetic interference (EMI). See

the Memory Map section (Register 0x5BA to Register 0x5C1 in

Table 36) for more details.

PLL

The PLL generates the serializer clock, which operates at the

JESD204B lane rate. The status of the PLL lock can be checked

in the PLL locked status bit (Register 0x501, Bit 7). This read

only bit lets the user know if the PLL has achieved a lock for the

specific setup. The JESD204B lane rate control, Bits[3:0] of

600

400

200

–200

–400

–600

–60

–40

–20

TIME (ps)

Figure 119. Digital Outputs Data Eye, External 100 Ω Terminations

at 16 Gbps

200

–200

–400

–600

–60

–40

–20

TIME (ps)

Figure 120. Digital Outputs Histogram, External 100 Ω Terminations

at 16 Gbps

–0.5

1–2

1–4

1–6

1–8

1–10

1–12

1–14

1–16

–0.4 –0.3 –0.2 –0.1

UIs

0.1

0.2

0.3

0.4

0.5

Figure 121. Digital Outputs Bathtub Curve, External 100 Ω Terminations

at 16 Gbps

AD9213 Datasheet(PDF) 59 Page - Analog Devices

AD9213 Datasheet(HTML) 59 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL