AD9213 datasheet(7/110 Pages) AD

7 / 110 page

Data Sheet

AD9213

Rev. A | Page 7 of 110

Parameter

Min

Typ

Max

Unit

LOGIC OUTPUT (SDIO, GPIO, FD)

Logic Compliance

CMOS

Voltage

Logic 1, Output Logic Current High (IOH) = 4 mA

SVDD2 − 0.45

Logic 0, Output Logic Current Low (IOL) = 4 mA

0.45

RESET (RSTB) INPUT

Logic Compliance

CMOS

Voltage

Logic 1

0.70 × SVDD2

Logic 0

0.30 × SVDD2

Input Resistance

kΩ

SWITCHING SPECIFICATIONS

Nominal supply voltages, specified maximum sampling rate, internal reference, AIN = −1.0 dBFS. Minimum/maximum specifications

represent performance at −20°C ≤ TJ ≤ +115°C, unless otherwise noted. Typical specifications represent performance at TJ = 70°C.

Table 4.

Parameter

Min

Typ

Max

Unit

CLOCK (CLK)

Maximum Clock Rate

10.25

GSPS

Minimum Clock Rate

2.5

GSPS

Clock Duty Cycle

% duty cycle

LATENCY

Pipeline Latency

367

Clock cycles

Fast Detect Latency (FD)

170

Clock cycles

OUTPUT PARAMETERS (SERDOUT_x[x], x = 0 to 15)

Logic Compliance

JESD204B

Differential Output Voltage

560

770

mV p-p

Differential Termination Impedance

100

120

Ω

Unit Interval (UI)1

62.5

588.2

Rise Time (tR) (20% to 80% into 100 Ω Load)

Fall Time (tF) (20% to 80% into 100 Ω Load)

Phase-Locked Loop (PLL) Lock Time

Lane Rate (Nonreturn to Zero)2

1.7

12.5

Gbps

WAKE-UP TIME

Standby

Power-Down

APERTURE

Delay (tA)

120

Uncertainty (Jitter, tJ)

(fS) rms

Baud rate = 1/UI. A subset of this range can be supported.

Default L = 16. This number can be changed based on the sample rate and decimation ratio.

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