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Data Sheet

AD9213

Rev. A | Page 35 of 110

DIGITAL DOWNCONVERTER (DDC)

The AD9213 includes one DDC that provides filtering and

reduce the output data rate. This digital processing section

includes a numerically controlled oscillator (NCO), multiple

decimating finite impulse response (FIR) filters, a gain stage, and

a complex to real conversion stage. Each processing block has

control lines that allow the block to be independently enabled

and disabled to provide the required processing function. The

DDC can be configured to output either real (I) data or

complex (Q) output data.

The DDC outputs a 16-bit stream. The converter number of

bits, N, is set to a default value of 12. In full bandwidth operation,

the ADC outputs are the 12-bit word followed by four zeros,

unless the PN tail bits or control bits are enabled.

DDC GENERAL DESCRIPTION

The DDC block extracts a portion of the full digital spectrum

captured by the ADC(s). These portions are intended for inter-

mediate frequency (IF) sampling or oversampled baseband

radios requiring wide bandwidth input signals.

The DDC block contains the following signal processing stages:

•

Frequency translation stage (optional)

•

Filtering stage

•

Gain stage (optional)

•

Complex to real conversion stage (optional)

Frequency Translation Stage (Optional)

This stage consists of a phase coherent NCO and quadrature

mixers that can be used for frequency translation real input

signal. The phase coherent NCO allows an infinite number of

frequency hops that are referenced back to a single synchronization

event, and includes 16 shadow registers for fast switching appli-

cations. This stage shifts a portion of the available digital

spectrum down to baseband.

Filtering Stage

After shifting down to baseband, this stage decimates the frequency

spectrum using multiple low pass FIR filters for rate conversion.

The decimation process lowers the output data rate, in turn

reducing the output interface rate.

Gain Stage (Optional)

Due to losses associated with mixing a real input signal down to

baseband, this stage compensates by adding 0 dB or 6 dB of gain

to the processed signal.

Complex to Real Conversion Stage (Optional)

When real outputs are necessary, this stage converts the complex

outputs back to real by performing a (fS)/4 mixing operation

and a filter operation to remove the complex component of the

signal.

Figure 92 shows the detailed block diagram of the DDCs

implemented in the AD9213.

Figure 93 shows an example usage of one of the four DDC

channels with a real input signal and four half-band filters

(HB4 + HB3 + HB2 + HB1) used. Figure 93 shows complex

(decimate by 16) and real (decimate by 8) output options.

ADC

SAMPLING

NCO + MIXER

(OPTIONAL)

TIMING

REFERENCE

TIMING

REFERENCE

NCO

CHANNEL

SELECTION

TRIG_x

DECIMATION

FILTERS

GAIN STAGE

(OPTIONAL)

COMPLEX

TO REAL

CONVERSION

(OPTIONAL)

JESD204B

TRANSMIT

INTERFACE

JESD204B

LANES AT

UP TO 16Gbps

SYNCHRONIZATION

CONTROL

CIRCUITS

NCO CHANNEL

SELECTION

CIRCUITS

SYSREF_x

MAP

CONTROL

GPIO[x] PINS

TIMING

REFERENCE

Figure 92. DDC Detailed Block Diagram

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