AD9213 datasheet(8/110 Pages) AD

8 / 110 page

AD9213

Data Sheet

Rev. A | Page 8 of 110

TIMING SPECIFICATIONS

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

SYSREF_x TIMING REQUIREMENTS1

tSU_SR

Device clock to SYSREF_P setup time

−65

tH_SR

Device clock to SYSREF_P hold time

SERIAL PORT INTERFACE (SPI)

TIMING REQUIREMENTS

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH

Minimum period that SCLK can be in a logic high state

tLOW

Minimum period that SCLK can be in a logic low state

tACCESS

Maximum time delay between falling edge of SCLK and output data valid

for a read operation

tDIS_SDIO

Time required for the SDIO pin to switch from an output to an input

relative to the CSB rising edge (not shown in Figure 3)

SYSREF_x setup and hold times are defined with respect to the rising SYSREF_x edge and rising clock edge. Positive setup time leads the clock edge. Negative hold

time also leads the clock edge. There are no SYSREF_x setup and hold requirements in averaged SYSREF_x mode, which is the primary JESD204B Subclass 1 mode for

the AD9213.

Timing Diagrams

CLK_P

CLK_N

SYSREF_P

SYSREF_N

tSU_SR

tH_SR

Figure 2. SYSREF_x Setup and Hold Timing Diagram

DON’T CARE

SDIO

SCLK

CSB

tDS

tDH

tHIGH

tLOW

tCLK

tACCESS

R/W

A14

A13

A12

A11

A10

Figure 3. Serial Port Interface Timing Diagram (MSB First)

AD9213 Datasheet(PDF) 8 Page - Analog Devices

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