AD9213 datasheet(65/110 Pages) AD

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Data Sheet

AD9213

Rev. A | Page 65 of 110

DETERMINISTIC LATENCY

Both ends of the JESD204B link contain various clock domains

distributed throughout each system. Data traversing from one

clock domain to a different clock domain can lead to ambiguous

delays in the JESD204B link. These ambiguities lead to non-

repeatable latencies across the link from one power cycle or link

reset to the next. Section 6 of the JESD204B specification

addresses the issue of deterministic latency with mechanisms

defined as Subclass 1 and Subclass 2.

The AD9213 supports JESD204B Subclass 0 and Subclass 1

operation. Register 0x525, Bit 5 sets the subclass mode for the

AD9213 and its default is set for Subclass 1 operating mode

(Register 0x525, Bit 5 = 1). If deterministic latency is not a

system requirement, Subclass 0 operation is recommended and

the SYSREF signal may not be required. Even in Subclass 0

mode, the SYSREF signal can required in an application where

multiple AD9213 devices must be synchronized with each

other.

SUBCLASS 0 OPERATION

If there is no requirement for multi-chip synchronization while

operating in subclass 0 mode (Register 0x525, Bit 5 = 0), the

SYSREF input can be left disconnected. In this mode, the

relationship of the JESD204B clocks between the JESD204B

transmitter and receiver are arbitrary but does not affect the

ability of the receiver to capture and align the lanes within the

link.

SUBCLASS 1 OPERATION

The JESD204B protocol organizes data samples into octets,

frames, and multiframes, as described in the Transport Layer

section of this data sheet. The LMFC is synchronous with the

beginnings of these multiframes. In Subclass 1 operation, the

SYSREF_x signal is used to synchronize the LMFCs for each

device in a link or across multiple links (within the AD9213,

SYSREF_x signal also synchronizes the internal sample

dividers). This is illustrated in Figure 122. The JESD204B

receiver uses the multiframe boundaries and buffering to

achieve consistent latency across lanes (or even multiple

devices), and also to achieve a fixed latency between power

cycles and link reset conditions.

The AD9213 features both averaged SYSREF and sampled

SYSREF modes for JESD204B Subclass 1 operation. Averaged

SYSREF mode is valid for all AD9213 sample rates. Sampled

SYSREF mode is valid for 2.5 GSPS to 3 GSPS. See the

Multichip Synchronization (MCS) section for details.

Deterministic Latency Requirements

Several key factors are required for achieving deterministic

latency in a JESD204B Subclass 1 system.



SYSREF_x signal distribution skew within the system must

be less than the desired uncertainty for the system.



SYSREF_x setup and hold time requirements must be met

for each device in the system. With the AD9213 averaged

SYSREF mode, there are no setup and hold time

requirements for the externally applied SYSREF_x signal.

References to SYSREF_x setup and hold times are in the

context of the sampled SYSREF mode.



The total latency variation across all lanes, links and

devices must be ≤1 LMFC periods (see Figure 122). This

includes both variable delays and the variation in fixed

delays from lane to lane, link to link, and device to device

in the system.

Setting Deterministic Latency Registers

The JESD204B receive buffer in the logic device buffers data

starting on the LMFC boundary. If the total link latency in the

system is near an integer multiple of the LMFC period, it is

possible that from one power cycle to the next, the data arrival

time at the receive buffer can straddle an LMFC boundary. To

ensure deterministic latency in this case, a phase adjustment of

the LMFC at either the transmitter or receiver will need to be

performed. Typically, adjustments to accommodate the receive

buffer are made to the LMFC of the receiver. In the AD9213,

this adjustment can be made using the LMFC offset register

(Register 0x50A, Bits[4:0]). This register delays the LMFC in

frame clock increments, depending on the F parameter (number

of octets per lane per frame). For F = 1, every fourth setting (0,

4, 8, …) results in a 1-frame clock shift. For F = 2, every other

setting (0, 2, 4, …) results in a 1-frame clock shift. For all other

values of F, each setting results in a 1-frame clock shift. Figure 123

shows that in the case where the link latency is near an LMFC

boundary, the local LMFC of the AD9213 can be delayed to

delay the data arrival time at the receiver. Figure 124 shows how

the LMFC of the receiver is delayed to accommodate the receive

buffer timing. Consult the applicable JESD204B receiver user

guide for details on making this adjustment. If the total latency

in the system is not near an integer multiple of the LMFC period

or if the appropriate adjustments have been made to the LMFC

phase at the clock source, it is still possible to have variable latency

from one power cycle to the next. In this case, check for the

possibility that the setup and hold time requirements for the

SYSREF_x signal are not being met. This can be checked by

reading the SYSREF setup/hold monitor register (Register 0x1509).

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