AD9213 datasheet(76/110 Pages) AD

76 / 110 page

AD9213

Data Sheet

Rev. A | Page 76 of 110

Address

Bits

Bit Name

Settings

Description

Default

Access

0x125

SMON_PERIOD_1

[7:0]

SMON_PERIOD[15:8]

2-Bit Value, Sets Number of Clock Cycles

that Signal Monitor Performs Operation.

24-bit period value over which the signal

monitor performs the peak detection. The

bit value must be in multiples of 16.

0x0

R/W

0x126

SMON_PERIOD_2

[7:0]

SMON_PERIOD[23:16]

2-Bit Value, Sets Number of Clock Cycles

that Signal Monitor Performs Operation.

24-bit period value over which the signal

monitor performs the peak detection. The

bit value must be in multiples of 16.

0x0

R/W

0x127

SMON_STATUS_CTRL

[7:5]

Reserved

Reserved.

0x0

SMON_PEAK_EN

Signal Monitor Peak Detector Enable.

0x0

R/W

0Disabled.

1Enabled.

[3:1]

SMON_STATUS_RDSEL

Signal Monitor Status Readback Selection.

0x1 for peak detector.

0x0

R/W

1 Peak detector data.

SMON_STATUS_UPDATE

A high transition on this signal causes the

status value to change in the register map.

When this bit field is pulled high, the

SMON_STATUS updates with the next value

of the peak magnitude.

0x0

R/W

0x128

SMON_SFRAMER

[7:2]

SMON_SFRAMER_INSEL

Signal Monitor Serial Framer Input

Selection.

0x0

R/W

2 Peak magnitude is sent through the frame.

SMON_SFRAMER_MODE

Signal Monitor Serial Framer Mode

Selection.

0x0

R/W

1 5-bit framer selection.

SMON_SFRAMER_EN

Signal Monitor Serial Framer Enable.

0x0

R/W

0Disabled.

1Enabled.

0x129

SMON_SYNC_CTRL

[7:2]

Reserved

Reserved.

0x0

SMON_SYNC_NEXT

SMON Next Synchronization Mode.

0x0

R/W

0 Continuous mode.

1 Next synchronization mode. In this mode,

only the next valid edge of SYSREF_x pin

synchronizes the SMON block. Subsequent

edges of the SYSREF_x pin are ignored. The

SMON_SYNC_EN bit clears when the next

SYSREF_x edge is found.

SMON_SYNC_EN

SMON Synchronization Enable.

0x0

R/W

0Disabled.

1 Enabled. When synchronization is enabled,

if SMON_SYNC_NEXT = 1, only the next

valid edge of the SYSREF_x pin synchronizes

the SMON block. Subsequent edges of the

SYSREF_x pin are ignored. This bit clears

when the next SYSREF_x edge is received.

0x131

SMON_CLK_EN

[7:1]

RESERVED

Reserved.

0x0

SMON_CLK_EN

SMON Output Clock Enable.

0x0

R/W

0Disabled.

1Enabled.

0x332

CLK_CHG_REQ

[7:5]

Reserved

Reserved.

0x0

[4:0]

CLKCHGREQ

Request Sample Clock Frequency Change.

0x0

R/W

0x500

PLL_CTRL

JTX_PLL_BYPASS_LOCK

Bypass PLL Lock Input.

0x0

R/W

[6:4]

Reserved

Reserved.

0x0

[3:0]

JTX_LOW_LINE_RATE

JESD Low Line Rate Selection.

0x0

R/W

0011 Lane rate = 13.6 Gbps to 16 Gbps.

0000 Lane rate = 6.8 Gbps to 13.6 Gbps.

0001 Lane rate = 3.4 Gbps to 6.8 Gbps.

0101 Lane rate = 1.7 Gbps to 3.4 Gbps.

AD9213 Datasheet(PDF) 76 Page - Analog Devices

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