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AD9213 Datasheet(PDF) 87 Page - Analog Devices

Part # AD9213
Description  12-Bit, 6 GSPS/10.25 GSPS, JESD204B, RF Analog-to-Digital Converter
PDF  110 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9213 Datasheet(HTML) 87 Page - Analog Devices

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Data Sheet
AD9213
Rev. A | Page 87 of 110
Address
Register Name
Bits
Bit Name
Settings
Description
Default
Access
0100 Logical Lane 4.
0101 Logical Lane 5.
0110 Logical Lane 6.
0111 Logical Lane 7.
1000 Logical Lane 8.
1001 Logical Lane 9.
1010 Logical Lane 10.
1011 Logical Lane 11.
1100 Logical Lane 12.
1101 Logical Lane 13.
1110 Logical Lane 14.
1111 Logical Lane 15 (default).
[3:0]
JTX_LANE_ASSIGN_14
Physical Lane 14 Assignment.
0xE
R/W
0000 Logical Lane 0.
0001 Logical Lane 1.
0010 Logical Lane 2.
0011 Logical Lane 3.
0100 Logical Lane 4.
0101 Logical Lane 5.
0110 Logical Lane 6.
0111 Logical Lane 7.
1000 Logical Lane 8.
1001 Logical Lane 9.
1010 Logical Lane 10.
1011 Logical Lane 11.
1100 Logical Lane 12.
1101 Logical Lane 13.
1110 Logical Lane 14 (default).
1111 Logical Lane 15.
0x547
JTX_QBF_STATUS
[7:0]
JTX_QBF_STATUS
QBF Status
0x7D
R
0x557
JTX_TEST_GEN_INV
[7:1]
Reserved
Reserved.
0x0
R
0
JTX_TEST_GEN_INV
JESD Test Generator Invert.
0x0
R/W
0 Normal test mode data.
1 Inverted test mode data.
0x558
CHIP_USR_PAT_1_7_0
[7:0]
CHIP_USR_PAT_1_7_0
CHIP_USR_PAT_1. 8 LSBs of User Pattern 1.
0x0
R/W
0x559
CHIP_USR_PAT_1_15_8
[7:0]
CHIP_USR_PAT_1_15_8
CHIP_USR_PAT_1. 8 MSBs of User Pattern 1.
0x0
R/W
0x55A
CHIP_USR_PAT_2_7_0
[7:0]
CHIP_USR_PAT_2_7_0
CHIP_USR_PAT_2. 8 LSBs of User Pattern 2.
0x0
R/W
0x55B
CHIP_USR_PAT_2_15_8
[7:0]
CHIP_USR_PAT_2_15_8
CHIP_USR_PAT_2. 8 MSBs of User Pattern 2.
0x0
R/W
0x55C
CHIP_USR_PAT_3_7_0
[7:0]
CHIP_USR_PAT_3_7_0
CHIP_USR_PAT_3. 8 LSBs of User Pattern 3.
0x0
R/W
0x55D
CHIP_USR_PAT_3_15_8
[7:0]
CHIP_USR_PAT_3_15_8
CHIP_USR_PAT_3. 8 MSBs of User Pattern 3.
0x0
R/W
0x55E
CHIP_USR_PAT_4_7_0
[7:0]
CHIP_USR_PAT_4_7_0
CHIP_USR_PAT_4. 8 LSBs of User Pattern 4.
0x0
R/W
0x55F
CHIP_USR_PAT_4_15_8
[7:0]
CHIP_USR_PAT_4_15_8
CHIP_USR_PAT_4. 8 MSBs of User Pattern 4.
0x0
R/W
0x560
SER_PARITY_RESET_EN1 [7:0]
SER_PARITY_RESET_
EN[7:0]
Parity Reset Enable, Bits[7:0].
0x0
R/W
0x561
SER_PARITY_RESET_EN2 [7:0]
SER_PARITY_RESET_
EN[15:8]
Parity Reset Enable, Bits[15:8].
0x0
R/W
0x564
SER_PARITY_ERR1
[7:0]
SER_PARITY_ERR[7:0]
Parity Error, Bits[7:0].
0x0
R
0x565
SER_PARITY_ERR2
[7:0]
SER_PARITY_ERR[15:8]
Parity Error, Bits[15:8].
0x0
R
0x570
PLL_ENABLE_CTRL
[7:5]
Reserved
Reserved.
0x0
R
4
LOLSTICKYCLEAR_
FORCE_LCPLL_RC
Clears Out Loss of Lock Bit
0x0
R/W
3
Reserved
Reserved.
0x0
R
2
LDSYNTH_FORCE_
LCPLL_ADC
A short 1 pulse starts VCO calibration, the
pulse width must be at least one reference
clock period. Allows user to perform a
calibration at will.
0x0
R/W
1
RESERVED
Reserved.
0x0
R
0
PWRUP_LCPLL
Power Up SERDES PLL.
0x1
R/W
0 SERDES PLL powered off.
1 SERDES PLL powered on.



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