AD9213 datasheet(67/110 Pages) AD

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Data Sheet

AD9213

Rev. A | Page 67 of 110

MULTICHIP SYNCHRONIZATION (MCS)

The AD9213 has a JESD204B Subclass 1 compatible SYSREF_x

input, which provides flexible options for synchronizing the

internal blocks of the AD9213. The SYSREF_x input is a source

synchronous system reference signal used to align the AD9213

LMFCs that enables multichip synchronization between multiple

AD9213s. The input clock divider, DDC, signal monitor block,

and JESD204B link can be synchronized using the SYSREF_x

input.

The AD9213 features a mode that averages the applied SYSREF

signal to create a stable internal version.

AVERAGED SYSREF MODE FOR MCS

In averaged SYSREF mode, the averaging function determines

the phase of the SYSREF_x signal. This information is used to

regenerate an internal version, and the averaged version is

tolerant to random jitter on external SYSREF_x signal and

synchronizes other downstream blocks within the ADC.

Multiple AD9213s each use the respective, internally

regenerated, averaged, local SYSREF signals.

The following are some characteristics of averaged SYSREF

synchronization:

•

Uses time to digital converters and filtering to recover

phase of the SYSREF signal and create a clean internal local

version.

•

Assumes the SYSREF signal is continuous or in pulse

trains.

•

No sampling issues due to setup/hold time violations.

•

Timing is recovered from the averaged waveform.

•

Extends JESD204B Subclass 1 to the full sample rate of the

AD9213.

•

Jitter tolerant. Jitter on the SYSREF signal is cleaned up by

averaging of SYSREF_x timing.

For the vast majority of sample rates at which the AD9213 is to

be used, averaged SYSREF mode is required for JESD204B

Subclass 1 operation.

SAMPLED SYSREF MODE

In sampled SYSREF mode, SYSREF_x operates as a standard

JESD204B Subclass 1 signal.

The following are some characteristics of sampled SYSREF_x

synchronization:

•

Synchronous sampling of SYSREF_x.

•

Must meet setup/hold time requirements for reliable

synchronization. This is increasingly difficult to achieve as

the sample rate increases.

•

SYSREF_x jitter must be much less than one sample clock

period. SYSREF_x coming from ASICs or FPGAs can have

significant jitter.

Because the setup and hold time requirements with respect to

the sample clock must be met for sampled SYSREF mode to

properly synchronize multiple devices, sampled SYSREF mode

does not operate properly at the full sample rate of the AD9213.

For multichip synchronization above 3 GSPS, averaged SYSREF

mode must be used.

HIGH SPEED CLOCK

INTENDED SYSREF

CORRUPTED SYSREF

DUE TO BAD SAMPLING

RECOVERED SYSREF

(FROM AVERAGING)

Figure 125. Recovered SYSREF_x

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