AD9213 datasheet(96/110 Pages) AD

96 / 110 page

AD9213

Data Sheet

Rev. A | Page 96 of 110

Address

Bits

Bit Name

Settings

Description

Default

Access

0 No overrange.

1 Overrange occurred.

0x624

OVR_CLR

[7:2]

Reserved

Reserved.

0x0

[1:0]

DFORMAT_OVR_CLR

Overrange Status Clear. Converter overrange

clear bit (active high). When an overrange

sticky bit has been set, it remains set until

explicitly cleared by writing 1 to the

corresponding DFORMAT_OVR_CLEAR[1:0]

bit. The DFORMAT_OVR_CLEAR[1:0] bit

must be cleared for further overrange to be

reported.

Bit 0: overrange sticky bit clear for Converter 0.

Bit 1: overrange sticky bit clear for Converter 1.

0x0

R/W

0x625

OUT_CHAN_SEL

[7:2]

Reserved

Reserved.

0x0

DFORMAT_CHAN_

REPLICATE

Output Channel Replication Control.

0x0

R/W

0 Unused converter outputs are zero.

1 Unused converter outputs are replicas of

valid converter outputs. For example, when

in high performance mode (CHIP_APP_

MODE = 0x0), Converter 1 is unused. When

this bit is set, Converter 0 is replicated on

Converter 1.

DFORMAT_CHAN_SWAP

Output Converter Channel Swap Control.

0x0

R/W

0 Normal channel ordering.

1 Channel Swap Enabled. Converter 0 and

Converter 1 are swapped.

0x626

OUT_RES

[7:5]

Reserved

Reserved.

0x0

DFORMAT_FBW_

DITHER_EN

DFORMAT Full Bandwidth (FBW) Dither

Enable. DFORMAT dither enable/disable for

mode.

0x0

R/W

0Dither disable.

1Dither enable.

[3:0]

DFORMAT_RES

Data Output Resolution.

0x0

R/W

0x0 16-bit resolution.

0x1 15-bit resolution.

…

0x9 7-bit resolution.

0xA to 0xF Reserved.

0x630

DDC_CTRL

[7:5]

Reserved

Reserved.

0x0

DDC0_C2R_EN

Complex to Real Enable.

0x0

R/W

0 Complex (I and Q) outputs contain valid data.

1 Real (I) output only. Complex to real enabled.

Uses extra fS/4 mixing to convert to real.

[3:2]

DDC0_IF_MODE

DDC Intermediate Frequency (IF) Mode.

0x0

R/W

00 Variable IF mode. Mixers and NCO enabled.

Use DDC_PHASE_INC[11:0] to digitally tune

the IF frequency.

01 0 Hz IF mode. Mixers bypassed and NCO

disabled. This mode infers clock gating cells

inside the Mixer and the NCO, and gates

combinatorial logic in the mixer multiplier

to save dynamic logic.

10 fS/4 Hz IF mode. Mixers and NCO are

enabled in special down-mixing by fS/4

mode. This power saving mode is described

in more detail in the JESD204B standard,

Section 1.1.6.1.6. fS/4 IF mode gain is

different in this mode than in variable IF

mode fS/4.

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