AD9213 datasheet(56/110 Pages) AD

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AD9213

Data Sheet

Rev. A | Page 56 of 110

DIGITAL OUTPUTS

INTRODUCTION TO THE JESD204B INTERFACE

The AD9213 digital outputs are designed to the JEDEC standard

JESD204B, serial interface for data converters. JESD204B is a

protocol to link the AD9213 to a digital processing device over

a serial interface with lane rates of up to 12.5 Gbps. The outputs

of the AD9213 exceed this, being good up through 16 Gbps.

The benefits of the JESD204B interface over LVDS include a

reduction in required board area for data interface routing, and

an ability to enable smaller packages for converter and logic

devices.

JESD204B OVERVIEW

The Data Format (DFORMAT) block formats data from

different sources within AD9213 and multiplexes this data to

the JESD204B transmitter interface (JTx). The JESD204B data

transmit block assembles the parallel data from the DFORMAT

block into frames and uses 8-bit/10-bit encoding as well as

optional scrambling to form serial output data. Lane synchro-

nization is supported through the use of special control characters

during the initial establishment of the link. Additional control

characters are embedded in the data stream to maintain synchro-

nization thereafter. A JESD204B receiver is required to complete

the serial link. For additional details on the JESD204B interface,

refer to the JESD204B standard.

The AD9213 DFORMAT block and JESD204B data transmit

block maps one physical ADC or, one or two virtual converters

(when DDC is enabled) over a link. A link can be configured to

use up to 16 JESD204B lanes. The JESD204B specification refers

to a number of parameters to define the link, and these parameters

must match between the JESD204B transmitter (the AD9213

output) and the JESD204B receiver (the logic device input).

The JESD204B link is described according to the following

parameters:

•

L is the number of lanes per converter device (lanes per

link). AD9213 value = 1, 2, 4, 8, 16, 3, 6, 12.

•

M is the number of converters per converter device (virtual

converters per link). AD9213 value = 1, 2.

•

F is the number of octets per frame. AD9213 value = 1, 2, 4.

•

N΄ is the number of bits per sample (JESD204B word size).

AD9213 value = 8, 12, or 16.

•

N is the converter resolution. AD9213 value = 7 to 16.

•

CS is the number of control bits per sample. AD9213

value = 0, 1, 2, or 3.

•

K is the number of frames per multiframe, K = 32 is

supported for all S.

•

K = 16, 32 is supported for configurations except when S = 1

and Register 0x630, Bit 4 = 1, in which case, only K = 32 is

supported.

•

S is the samples transmitted per single converter per frame

cycle. AD9213 value = set automatically based on L, M, F,

and N΄.

•

HD is the high density mode. AD9213 = set automatically

based on L, M, F, and N΄.

•

CF is the number of control words per frame clock cycle

per converter device. AD9213 value = 0.

Figure 114 shows a simplified block diagram of the AD9213

JESD204B link. By default, the AD9213 is configured as

one converter feeding all 16 lanes.

By default in the AD9213, the 12-bit converter word is broken

into two octets (8 bits of data). Bit 11 (MSB) through Bit 4 are in

the first octet. The second octet contains Bit 3 through Bit 0

(LSB) and 4 tail bits. The tail bits can be configured as zeros or a

pseudorandom number sequence. The tail bits can also be replaced

with control bits indicating overrange, SYSREF_x, or fast detect

output.

The two resulting octets can be scrambled. Scrambling is

optional. However, it is recommended to avoid spectral peaks

when transmitting similar digital data patterns. The scrambler

uses a self-synchronizing, polynomial-based algorithm defined

by the equation 1 + x14 + x15. The descrambler in the receiver is

a self-synchronizing version of the scrambler polynomial.

The two octets are then encoded with an 8-bit/10-bit encoder.

The 8-bit/10-bit encoder works by taking eight bits of data (an

octet) and encoding them into a 10-bit symbol. Figure 115

shows how the 12-bit data is taken from the ADC, how the tail

bits are added, how the two octets are scrambled, and how the

octets are encoded into two 10-bit symbols. Figure 115 shows the

default data format.

ADC

SYSREF_x

SYNCINB_x

CONVERTER

INPUT

SERDOUT_N0

SERDOUT_P0

SERDOUT_N1

SERDOUT_P1

SERDOUT_N14

SERDOUT_P14

SERDOUT_N15

SERDOUT_P15

LANE MUX

AND MAPPING

JESD204B LINK

CONTROL

(L.M.F)

MUX/

DFORMAT

Figure 114. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x606 = 0x00)

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