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AD9213 Datasheet(PDF) 99 Page - Analog Devices |
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AD9213 Datasheet(HTML) 99 Page - Analog Devices |
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99 / 110 page  Data Sheet AD9213 Rev. A | Page 99 of 110 Address Register Name Bits Bit Name Settings Description Default Access 0x642 DDC_PHASE_INC_ FRAC_A2 [7:0] DDC0_PHASE_INC_ FRAC_A2 Phase Increment Numerator, Bits [23:16]. Twos complement numerator correction term for modulus phase accumulator. 0x0 R/W 0x643 DDC_PHASE_INC_ FRAC_A3 [7:0] DDC0_PHASE_INC_ FRAC_A3 Phase Increment Numerator, Bits [31:24]. Twos complement numerator correction term for modulus phase accumulator. 0x0 R/W 0x644 DDC_PHASE_INC_ FRAC_A4 [7:0] DDC0_PHASE_INC_ FRAC_A4 Phase Increment Numerator, Bits [39:32]. Twos complement numerator correction term for modulus phase accumulator. 0x0 R/W 0x645 DDC_PHASE_INC_ FRAC_A5 [7:0] DDC0_PHASE_INC_ FRAC_A5 Phase Increment Numerator, Bits [47:40] Twos complement numerator correction term for modulus phase accumulator. 0x0 R/W 0x646 DDC_PHASE_INC_ FRAC_B0 [7:0] DDC0_PHASE_INC_ FRAC_B0 Phase Increment Denominator, Bits [7:0]. Twos complement denominator correction term for modulus phase accumulator. 0x0 R/W 0x647 DDC_PHASE_INC_ FRAC_B1 [7:0] DDC0_PHASE_INC_ FRAC_B1 Phase Increment Denominator, Bits [15:8]. Twos complement denominator correction term for modulus phase accumulator. 0x0 R/W 0x648 DDC_PHASE_INC_ FRAC_B2 [7:0] DDC0_PHASE_INC_ FRAC_B2 Phase Increment Denominator, Bits [23:16]. Twos complement denominator correction term for modulus phase accumulator. 0x0 R/W 0x649 DDC_PHASE_INC_ FRAC_B3 [7:0] DDC0_PHASE_INC_ FRAC_B3 Phase Increment Denominator, Bits [31:24]. Twos complement denominator correction term for modulus phase accumulator. 0x0 R/W 0x64A DDC_PHASE_INC_ FRAC_B4 [7:0] DDC0_PHASE_INC_ FRAC_B4 Phase Increment Denominator, Bits [39:32]. Twos complement denominator correction term for modulus phase accumulator. 0x0 R/W 0x64B DDC_PHASE_INC_ FRAC_B5 [7:0] DDC0_PHASE_INC_ FRAC_B5 Phase Increment Denominator, Bits [47:40]. Twos complement denominator correction term for modulus phase accumulator. 0x0 R/W 0x64C DDC_TRANSFER_CTRL [7:1] Reserved Reserved. 0x0 R 0 DDC0_CHIP_TRANSFER DDC Chip Transfer. Note that this bit updates the DDC phase increment and phase offset registers when DDC_PHASE_UPDATE_MODE = 1 and DDC_GPIO_CHIP_TRANSFER_MODE = 0. 0x0 R/W 0Do nothing. 1 Synchronizes data transfer from master registers to slave registers. 0x64D DDC_TRANSFER_STATUS [7:1] Reserved Reserved. 0x0 R 0 DDC0_CHIP_TRANSFER_ STATUS DDC Chip Transfer Status Bit. 0x0 R 0 Data transfer from master register to slave register is complete. 1 Indicates the data transfer is not requested or not completed. 0x650 MOD_NCO_PHASE_ ERROR_LOAD_REG0 [7:0] MOD_NCO_PHASE_ ERROR_LOAD_ VALUE[7:0] MOD NCO Phase Error Value. 0x0 R/W 0x651 MOD_NCO_PHASE_ ERROR_LOAD_REG1 [7:0] MOD_NCO_PHASE_ ERROR_LOAD_ VALUE[15:8] MOD NCO Phase Error Value. 0x0 R/W 0x652 MOD_NCO_PHASE_ ERROR_LOAD_REG2 [7:0] MOD_NCO_PHASE_ ERROR_LOAD_ VALUE[23:16] MOD NCO Phase Error Value. 0x0 R/W 0x653 MOD_NCO_PHASE_ ERROR_LOAD_REG3 [7:0] MOD_NCO_PHASE_ ERROR_LOAD_ VALUE[31:24] MOD NCO Phase Error Value. 0x0 R/W 0x654 MOD_NCO_PHASE_ ERROR_LOAD_REG4 [7:0] MOD_NCO_PHASE_ ERROR_LOAD_ VALUE[39:32] MOD NCO Phase Error Value. 0x0 R/W 0x655 MOD_NCO_PHASE_ ERROR_LOAD_REG5 [7:0] MOD_NCO_PHASE_ ERROR_LOAD_ VALUE[47:40] MOD NCO Phase Error Value. 0x0 R/W |
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