AD9213 datasheet(103/110 Pages) AD

103 / 110 page

Data Sheet

AD9213

Rev. A | Page 103 of 110

Address

Bits

Bit Name

Settings

Description

Default

Access

SUPMON_VDDD_

SPI_1P8

2 V Digital Supply Monitor for SPI Pads.

0x1

SUPMON_VDDA_

REF_2P0

2 V Analog Supply Monitor for Reference.

0x1

SUPMON_VDDA_

BUF_2P0

2 V Analog Supply Monitor for Buffer

0x1

0x1514

SUPPLY_MON3

[7:2]

Reserved

Reserved.

0x0

SUPMON_VEEA_NEG1P0

−1 V Analog Supply Monitor.

0x1

SUPMON_VEEA_BUF_

NEG1P0

−1 V Analog Supply Monitor for Buffer.

0x1

0x1515

PDOWN_CTRL

[7:3]

PDB_REF_NOHCLK

Power-Down for Reference.

0x1F

R/W

SPI_PDB_CLKBUF

Power-Down for Clock Buffer.

0x1

R/W

STDBY_CHIP

Standby Chip.

0x0

R/W

PD_CHIP

Power Down Chip.

0x0

R/W

0x1516

SPI_EN_FDLY_SYS

[7:2]

Reserved

Reserved.

0x0

SPI_EN_SFDLY_SYS

Super Fine Delay Cell Enable Bit for System

Clock.

0x0

R/W

0Disabled.

1 Enabled (along with half fine delay cell).

SPI_EN_FDLY_SYS

Fine Delay Cell enable Bit for System Clock.

Two halves fine delay cells in series. Each

has 24 steps adjustments.

0x0

R/W

0Disabled.

1 Enabled (two halves fine delay cells).

0x1517

SPI_TRM_FINE_DLY_SYS [7:0]

SPI_TRM_FINE_DLY_SYS

Clock Fine Adjustment for System Clock.

This is an unsigned control to adjust the

system clock skew in 1.1 ps per step with

48 total steps. These bits are used only when

Minimum delay = 0, maximum delay = 48.

0x0

R/W

0x1518

SPI_TRM_SUPER_FINE_

DLY_SYS

[7:0]

SPI_TRM_SUPER_FINE_

DLY_SYS

Clock super fine delay SYS clock adjustment.

This is an unsigned control to adjust the

system clock skew in 16 fS/step with 255 total

steps. These bits are only used when

Bit 0 = 0. Minimum delay = 0, maximum

delay = 255.

0x0

R/W

0x1519

SPI_SFDC_BYPASS_SYS

[7:1]

Reserved

Reserved.

0x0

SPI_SFDC_BYPASS_SYS

Super Fine Delay Cell Bypassed for the

system clock. This bit works in conjunction

with the SPI_EN_SFDLY_SYS bit. When

SPI_EN_SFDLY_SYS = 0, SPI_SFDC_BYPASS_

SYS = 0 or 1 (don't care). When SPI_EN_

SFDLY_SYS = 1, SPI_SFDC_BYPASS_SYS = 1

super fine delay cell bypassed for the

system clock.

0x0

R/W

0x151A

EN_VCM_MODE

[7:2]

Reserved

Reserved.

0x0

[1:0]

EN_VCM_MODE

VCM Enable Mode Control.

0x1

R/W

00 Internal and External VCM control buffers

disabled.

01 Startup. Internal VCM control buffer

enabled.

10 External VCM control buffer enabled.

11 Internal and External VCM control buffers

enabled. Auxiliary mode.

AD9213 Datasheet(PDF) 103 Page - Analog Devices

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