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AD9213 Datasheet(PDF) 101 Page - Analog Devices |
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AD9213 Datasheet(HTML) 101 Page - Analog Devices |
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101 / 110 page  Data Sheet AD9213 Rev. A | Page 101 of 110 Address Register Name Bits Bit Name Settings Description Default Access 0x671 TIMESTAMP_READ_CTRL [7:1] Reserved Reserved. 0x0 R 0 TIMESTAMP_READ_ENA BLE Timestamp Read Enable. Rising edge on time stamp read enable is detected and then timestamp counter data is latched. This stored time stamp data is used for timestamp status read. 0x0 R/W 0x672 TIMESTAMP_COUNTER_ REG0 [7:0] TIMESTAMP[7:0] Time Stamp Counter Value, Bits[7:0]. 0x0 R 0x673 TIMESTAMP_COUNTER_ REG1 [7:0] TIMESTAMP[15:8] Time Stamp Counter Value, Bits[15:8]. 0x0 R 0x674 TIMESTAMP_COUNTER_ REG2 [7:0] TIMESTAMP[23:16] Time Stamp Counter Value, Bits[23:16]. 0x0 R 0x675 TIMESTAMP_COUNTER_ REG3 [7:0] TIMESTAMP[31:24] Time Stamp Counter Value, Bits[31:24]. 0x0 R 0x676 TIMESTAMP_COUNTER_ REG4 [7:0] TIMESTAMP[39:32] Time Stamp Counter Value, Bits[39:32]. 0x0 R 0x677 TIMESTAMP_COUNTER_ REG5 [7:0] TIMESTAMP[47:40] Time Stamp Counter Value, Bits[47:40]. 0x0 R 0x678 TIMESTAMP_COUNTER_ REG6 [7:0] TIMESTAMP[55:48] Time Stamp Counter Value, Bits[55:48]. 0x0 R 0x679 TIMESTAMP_COUNTER_ REG7 [7:0] TIMESTAMP[63:56] Time Stamp Counter Value, Bits[63:56]. 0x0 R 0x681 JTX_CLK [7:5] Reserved Reserved. 0x0 R 4 JTX_CLK_EN JTx Clock Enable Selection. 0x0 R/W 0 DDC and JTx clocks disabled. 1 DDC and JTx clocks enabled. [3:0] Reserved Reserved. 0x0 R 0x690 SYSREF_DELAY [7:0] SYSREF_PROGDELAY Programmable Delay on SYSREF_x Path to DDC NCO. 8-bit delay in terms of sampling clock. 0x0 R/W 0x691 TRIG_DELAY [7:0] TRIG_PROGDELAY Programmable Delay on TRIG_x Path to DDC NCO. 8-bit delay in terms of sampling clock. 0x0 R/W 0x692 TIMESTAMP_DELAY [7:0] TIMESTAMP_PROGDELAY Programmable Delay on Time Stamp Path in DFORMAT. 8-bit delay in terms of sampling clock. 0x0 R/W 0x693 SYSREF_RESYNC [7:1] Reserved Reserved. 0x0 R 0 SYSREF_RESYNC SYSREF_x Resynchronization Mode Enable. SYSREF_x timestamp mode is for Subclass 0 operation. All Subclass 1 operation for deterministic latency must set to Bit 0 = 1 (SYSREF_x resynchronization mode enabled). 0x0 R/W 0 SYSREF_x timestamp mode enabled. 1 SYSREF_x resynchronization mode enabled. 0x1507 RESET_CTRL [7:5] Reserved Reserved. 0x2 R 4 RESET_JTX Reset JTx Block. 0x0 R/W 3 Reserved Reserved. 0x0 R/W 2 RESET_DPATH Reset Datapath. Apply to main digital. 0x0 R/W 1 RESET_DIG_ANA Reset Digital Blocks and Registers in the Analog Section. 0x0 R/W 0 RESET_ANA Reset Analog Section. 0x0 R/W 0x1508 SYSREF_CTRL [7:2] Reserved Reserved. 0x0 R 1 SYSREF_TRANSITION_SEL SYSREF_x Transition Selection. 0x0 R/W 0 SYSREF_x is valid on low to high transitions using selected CLK_x edge. 1 SYSREF is valid on high to low transitions using selected CLK_x edge. 0 SYSREF_EDGE_SEL SYSREF_x Capture Edge Selection. 0x0 R/W 0 Captured on rising edge of CLK_x input. 1 Captured on falling edge of CLK_x input. 0x1509 SYSREF_STATUS [7:4] SYSREF_HOLD_STATUS Gives Status of Hold Capture Window. 0xF R [3:0] SYSREF_SETUP_STATUS Gives Status of Setup Capture Window. 0x8 R |
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