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AD9213 Datasheet(PDF) 102 Page - Analog Devices |
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AD9213 Datasheet(HTML) 102 Page - Analog Devices |
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102 / 110 page  AD9213 Data Sheet Rev. A | Page 102 of 110 Address Register Name Bits Bit Name Settings Description Default Access 0x150A LVDS_SEL [7:2] Reserved Reserved. 0x0 R 1 TRIG_RX_LVDS_SEL Switch Between LVDS and Differential CMOS Input Modes for TRIG_x. 0x0 R/W 0 Differential CMOS selected. 1 LVDS selected. 0 SYSREF_RX_LVDS_SEL Switch between LVDS and Differential CMOS Input Modes for SYSREF_x. 0x0 R/W 0 Differential CMOS selected 1 LVDS selected 0x150C SPI_EN_DCS [7:1] Reserved Reserved. 0x0 R 0 SPI_EN_DCS Duty Cycle Stabilizer. 0x0 R/W 0Disable. 1Enable. 0x150D SPI_EN_FDLY [7:2] Reserved Reserved. 0x0 R 1 SPI_EN_SFDLY Super Fine Delay Cell enable bit. 0x0 R/W 0Disabled. 1 Enabled (along with half fine delay cell). 0 SPI_EN_FDLY Fine Delay Cell Enable Bit. Two halves fine delay cells in series. Each has 24 steps adjustments. 0x0 R/W 0Disabled. 1 Enabled (two halves fine delay cells). 0x150E SPI_TRM_FINE_DLY [7:0] SPI_TRM_FINE_DLY Clock Fine Adjustment. This is an unsigned control to adjust sampling clock skew in 1.1 ps per step with 48 total steps. These bits are used only when Register 0x150D, Bit 1 or Bit 0 are set to 1. Minimum delay = 0, maximum delay = 48. 0x0 R/W 0x150F SPI_TRM_SUPER_FINE_ DLY [7:0] SPI_TRM_SUPER_ FINE_DLY Clock Super Fine Delay Adjustment. This is an unsigned control to adjust sampling clock skew in 16 fS/step with 255 total steps. These bits are only used when Register 0x150D, Bit 1 = 1, Register 0x1510, Bit 0 = 0. Minimum delay = 0, maximum delay = 255. 0x0 R/W 0x1510 SPI_SFDC_BYPASS [7:1] Reserved Reserved. 0x0 R 0 SPI_SFDC_BYPASS Super Fine Delay Cell Bypassed. This bit works in conjunction with SPI_EN_SFDLY bit. When SPI_EN_SFDLY = 0, SPI_SFDC_ BYPASS = 0 or 1 (don't care). When SPI_EN_ SFDLY = 1, SPI_SFDC_BYPASS = 1 super fine delay cell bypassed. 0x0 R/W 0x1511 BKEND_TOP_GAIN_ADJ [7:1] Reserved Reserved. 0x0 R 0 GAIN_2X Setting this Bit to 1 Doubles the Data at the Output. 0x0 R/W 0x1512 SUPPLY_MON1 [7:6] Reserved Reserved. 0x0 R 5 SUPMON_VTTPHY_ SER_0P9 1 V Supply Monitor for SERDES. 0x1 R 4 SUPMON_VDDSYNTH_ LCPLL_0P9 1 V Supply Monitor for JESD204B Synthesizer. 0x1 R 3 SUPMON_VDDD_ LCPLL_0P9 1 V Digital Supply Monitor for JESD PLL. 0x1 R 2 SUPMON_VDDA_ REFADC_1P0 1 V Analog Supply Monitor for Reference ADC. 0x1 R 1 SUPMON_VDDA_ CLK_1P0 1 V Analog Supply Monitor for Clock. 0x1 R 0 SUPMON_VDDA_1P0 1 V Analog Supply Monitor. 0x1 R 0x1513 SUPPLY_MON2 [7:5] Reserved Reserved. 0x0 R 4 SUPMON_VDDA_ TMU_1P8 2 V Analog Supply Monitor for TMU. 0x1 R 3 SUPMON_VDDLDO_ LCPLL_1P8 2 V Supply Monitor for JESD204B LDO. 0x1 R |
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