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AD9213 Datasheet(PDF) 100 Page - Analog Devices |
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AD9213 Datasheet(HTML) 100 Page - Analog Devices |
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100 / 110 page  AD9213 Data Sheet Rev. A | Page 100 of 110 Address Register Name Bits Bit Name Settings Description Default Access 0x656 MOD_NCO_PHASE_ ERROR_LOAD_CTRL [7:1] Reserved Reserved. 0x0 R 0 MOD_NCO_PHASE_ ERROR_LOAD_ENABLE MOD NCO Phase Error Load Enable. 0x0 R/W 0x657 MOD_NCO_PHASE_ ERROR_LOAD_STATUS [7:3] Reserved Reserved. 0x0 R 2 MOD_NCO_PHASE_ ERROR_LOAD_STATUS MOD NCO Phase Error Load Status. 0x0 R [1:0] Reserved Reserved. 0x0 R 0x65F DDC_PSW_0 [7:0] DDC0_PSW0 DDC Profile Select Word. (PSW), Bits[7:0]. The PSW specifies the rollover point for the profile select timer (PST) in encode samples. The channel selection counter increments when the PST rolls over to zero, and channel selection occurs through the PST. 0x0 R/W 0x660 DDC_PSW_1 [7:0] DDC0_PSW1 DDC PSW, Bits[15:8]. The PSW specifies the rollover point for the PST in encode samples. The channel selection counter increments when the PST rolls over to zero, and channel selection occurs through the PST. 0x0 R/W 0x661 DDC_PSW_2 [7:0] DDC0_PSW2 DDC PSW, Bits[23:16]. The PSW specifies the rollover point for the PST in encode samples. The channel selection counter increments when the PST rolls over to zero, and channel selection occurs through the PST. 0x0 R/W 0x662 DDC_PSW_3 [7:0] DDC0_PSW3 DDC PSW, Bits[31:24]. The PSW specifies the rollover point for the PST in encode samples. The channel selection counter increments when the PST rolls over to zero, and channel selection occurs through the PST. 0x0 R/W 0x663 DDC_PSW_4 [7:0] DDC0_PSW4 DDC PSW, Bits[39:23]. The PSW specifies the rollover point for the PST in encode samples. The channel selection counter increments when the PST rolls over to zero, and channel selection occurs through the PST. 0x0 R/W 0x664 DDC_PSW_5 [7:0] DDC0_PSW5 DDC PSW, Bits[47:40]. The PSW specifies the rollover point for the PST in encode samples. The channel selection counter increments when the PST rolls over to zero, and channel selection occurs through the PST. 0x0 R/W 0x665 DDC_ACTIVE_PHASE_ INC0 [7:0] DDC0_ACTIVE_PHASE_ INC0 NCO Active Phase Increment Value, Bits[7:0]. 0x0 R 0x666 DDC_ACTIVE_PHASE_ INC1 [7:0] DDC0_ACTIVE_PHASE_ INC1 NCO Active Phase Increment Value, Bits[15:8]. 0x0 R 0x667 DDC_ACTIVE_PHASE_ INC2 [7:0] DDC0_ACTIVE_PHASE_ INC2 NCO Active Phase Increment Value, Bits[23:16]. 0x0 R 0x668 DDC_ACTIVE_PHASE_ INC3 [7:0] DDC0_ACTIVE_PHASE_ INC3 NCO Active Phase Increment Value, Bits[31:24]. 0x0 R 0x669 DDC_ACTIVE_PHASE_ INC4 [7:0] DDC0_ACTIVE_PHASE_ INC4 NCO Active Phase Increment Value, Bits[39:32]. 0x0 R 0x66A DDC_ACTIVE_PHASE_ INC5 [7:0] DDC0_ACTIVE_PHASE_ INC5 NCO Active Phase Increment Value, Bits[47:40]. 0x0 R 0x66B DDC_ACTIVE_PHASE_ OFFSET0 [7:0] DDC0_ACTIVE_PHASE_ OFFSET0 NCO Active Phase Increment Value, Bits[7:0]. 0x0 R 0x66C DDC_ACTIVE_PHASE_ OFFSET1 [7:0] DDC0_ACTIVE_PHASE_ OFFSET1 NCO Active Phase Increment Value, Bits[15:8]. 0x0 R 0x66D DDC_ACTIVE_PHASE_ OFFSET2 [7:0] DDC0_ACTIVE_PHASE_ OFFSET2 NCO Active Phase Increment Value, Bits[23:16]. 0x0 R 0x66E DDC_ACTIVE_PHASE_ OFFSET3 [7:0] DDC0_ACTIVE_PHASE_ OFFSET3 NCO Active Phase Increment Value, Bits[31:24]. 0x0 R 0x66F DDC_ACTIVE_PHASE_ OFFSET4 [7:0] DDC0_ACTIVE_PHASE_ OFFSET4 NCO Active Phase Increment Value, Bits[39:32]. 0x0 R 0x670 DDC_ACTIVE_PHASE_ OFFSET5 [7:0] DDC0_ACTIVE_PHASE_ OFFSET5 NCO Active Phase Increment Value, Bits[47:40]. 0x0 R |
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