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AD9213 Datasheet(PDF) 70 Page - Analog Devices |
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AD9213 Datasheet(HTML) 70 Page - Analog Devices |
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70 / 110 page  AD9213 Data Sheet Rev. A | Page 70 of 110 TEST MODES JESD204B TEST MODES The AD9213 has flexible test modes in the JESD204B block. These test modes are listed in Register 0x505 and Register 0x506. These test patterns can be injected at various points along the output datapath. These test injection points shown in Figure 115 illustrate the various test modes available in the JESD204B block. For the AD9213, a transition from test modes (Register 0x505 ≠ 0x00) to normal mode (Register 0x505 = 0x00) requires an SPI soft reset. This is done by writing 0x81 to Register 0x0000 (self cleared). Transport Layer Sample Test Mode The transport layer samples are implemented in the AD9213 as defined by Section 5.1.6.3 in the JEDEC JESD204B specification. These tests are shown in Register 0x503, Bit 5. The test pattern is equivalent to the raw samples from the ADC. Interface Test Modes The interface test modes are described in Register 0x505, Bits[3:0]. These test modes are also explained in Table 31. The interface tests can be injected at various points along the data. See Figure 115 for more information on the test injection points. Register 0x505, Bits[5:4] show where these tests are injected. Table 32 and Table 33 show examples of some of the test modes when injected at the JESD204B sample input, PHY 10-bit input, and scrambler 8-bit input. UPx in the tables represent the user pattern control bits from the customer register map. DATA LINK LAYER TEST MODES The data link layer test modes are implemented in the AD9213 as defined by Section 5.3.3.8.2 in the JEDEC JESD204B specification. These tests are shown in Register 0x506, Bits[2:0]. Test patterns inserted at this point are useful for verifying the functionality of the data link layer. When the data link layer test modes are enabled, disable SYNCINB± by writing 0xC0 to Register 0x504. Table 30. JESD204B Interface Test Modes Output Test Mode Bit Sequence Pattern Name Expression Default 0000 Off (default) Not applicable Not applicable 0001 Alternating checker board 0x5555, 0xAAAA, 0x5555, … Not applicable 0010 1/0 word toggle 0x0000, 0xFFFF, 0x0000, … Not applicable 0011 31-bit PN sequence x31 + x28 + 1 0x0003AFFF 0100 23-bit PN sequence x23 + x18 + 1 0x003AFF 0101 15-bit PN sequence x15 + x14 + 1 0x03AF 0110 9-bit PN sequence x9 + x5 + 1 0x092 0111 7-bit PN sequence x7 + x6 + 1 0x07 1000 Ramp output (x) % 216 Ramp size depends on test injection point 1110 Continuous/repeat user test Register 0x558 to Register 0x55F User Pattern 1 to User Pattern 4, then repeat 1111 Single user test Register 0x558 to Register 0x55F User Pattern 1 to User Pattern 4, then zeros Table 31. JESD204B Sample Input for M = 1, S = 16, N' = 16 (Register 0x505, Bits[5:4] = 'b00) Frame Number Converter Number Sample Number Alternating Checkerboard 1/0 Word Toggle Ramp PN9 PN23 User Repeat User Single 0 0 0 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 1 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 2 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 3 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 4 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 5 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 6 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 7 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 8 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 9 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 10 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 11 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 12 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 13 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 14 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 15 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] |
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