TW2864D datasheet(30/110 Pages) RENESAS

30 / 110 page

TW2864

FN7745 Rev. 0.00

Page 30 of 110

September 28, 2012

AUDIO CODEC

The audio codec in the TW2864 is composed of 4 audio Analog-to-Digital converters, 1 Digital-to-Analog converter,

audio mixer, digital serial audio interface and audio detector, as shown in Figure 15. The TW2864 can accept 4

analog audio signals and 1 digital serial audio data and produce 1 mixing analog audio signal and 2 digital serial

audio data.

ADC

AIN1

I2S Encoder

ACLKR

ASYNR

ADATR

ADATM

I2S Decoder

ACLKP

ASYNP

ADATP

AOUT

DAC

MIX

MUTE

ADC

AIN2

MUTE

ADC

AIN3

MUTE

ADC

AIN4

MUTE

RATIO

MUTE

Audio

Detector

FIGURE 15. BLOCK DIAGRAM OF AUDIO CODEC

The level of analog audio input signal AIN0 ~ AIN4 can be adjusted respectively by internal programmable gain

amplifiers that are defined via the AIGAIN1, AIGAIN2, AIGAIN3 and AIGAIN4 registers and then sampled by each

Analog-to-Digital converters. The digital serial audio input data through the ACLKP, ASYNP and ADATP pin are used

for playback function. To record audio data, the TW2864 provides the digital serial audio output via the ACLKR,

ASYNR and ADATR pin.

The TW2864 can mix all of audio inputs including analog audio signal and digital audio data according to the

predefined mixing ratio for each audio via the MIX_RATIO1 ~ MIX_RATIO4 and MIX_RATIOP registers. This mixing

audio output can be provided through the analog and digital interfaces. The embedded audio Digital-to-Analog

converter supports the analog mixing audio output whose level can be controlled by programmable gain amplifier via

the AOGAIN register. The ADATM pin supports the digital mixing audio output and its digital serial audio timings are

provided through the ACLKR and ASYNR pins that are shared with the digital serial audio record timing pins.

AUDIO CLOCK MASTER/SLAVE MODE

The TW2864 has two types of Audio Clock modes. If ACLKRMASTER register is set to 1,fs audio sample date is

processed from 256xfs audio clock internal ACKG (Audio Clock Generator) generates. In this master mode,

ACLKR/ASYNR pins are output mode. ASYNROEN register for ASYNR pin should be set to 0(output enable mode).If

ACLKRMASTER register is set to 0,fs audio sample rate is processed from 256xfs audio clock on ACLKR pin

input.256xfs audio clock should be connected to ACLKR pin from external master clock source in this slave mode.

TW2864D Datasheet(PDF) 30 Page - Renesas Technology Corp

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