TW2864D datasheet(93/110 Pages) RENESAS

93 / 110 page

TW2864

FN7745 Rev. 0.00

Page 93 of 110

September 28, 2012

Index

Clock Output Control

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

0xFA

VSCL_ENA

CLKN_

OEB

CLKP_

OEB

CLKN_MD

CLKP_MD

VSCL_ENA(REV_ID>=1 TW2864 only)

Enable the vertical scaler for 4x CIF time-multiplexed format with 54MHz.

Full size for vertical direction (default)

Half size for vertical direction

Control the tri-state of output pin

Outputs are Tri-state except clock output (CLKPO, CLKNO) pin

(default)

Outputs are enabled

CLKN_OEB

Control the tri-state of CLKNO pin

Output is enabled (default)

Output is Tri-state

CLKP_OEB

Control the tri-state of CLKPO pin

Output is enabled (default)

Output is Tri-state

CLKN_MD

Control the clock frequency of CLKNO/CLKPO pin

CLKP_MD

CLKI Input Freq / 4 Clock for TW2864A/TW2864C(default)

CLKI Input Freq / 2 Clock for TW2864B/TW2864D(default)

CLKI Input Freq / 2 Clock for TW2864A/TW2864C

CLKI Input Freq Clock for TW2864B/TW2864D

CLKI Input Freq Clock for TW2864A/TW2864B/TW2864C/TW2864D

always 0 value

[REV_ID>=1 TW2864 only]

If Single Channel Clock-In mode is selected,

0,1,2 CLKI Input Freq Clock for TW2864A/TW2864B/TW2864C/TW2864D

always 0 value

TW2864D Datasheet(PDF) 93 Page - Renesas Technology Corp

TW2864D Datasheet(HTML) 93 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL