TW2864D datasheet(27/110 Pages) RENESAS

27 / 110 page

TW2864

FN7745 Rev. 0.00

Page 27 of 110

September 28, 2012

OUTPUT ENABLING ACT

After power-up, the TW2864 registers have unknown values. The RSTB pin must be asserted and released to bring all

registers to its default values. After reset, the TW2864 data outputs are tri-stated. The OE register should be written

after reset to enable outputs desired.

VIDEO OUTPUT CHANNEL SELECTION

If CHMDn[1:0] in Reg0xCA is set to 0hex,MAINCHn[1:0] in Reg0xCD selects one number of Video Channels to be

output on VDn[7:0] pin as Single Channel ITU-R BT.656(D1) Format output.If CHMDn[1:0] in Reg0xCA is set to

1hex,MAINCHn[1:0] in Reg0xCD and SELCHn[1:0] in Reg0xCC select two numbers of Video Channels to be output on

VDn[7:0] pin as Two Channel ITU-R BT.656(D1) Time-multiplexed Format output.If CHMDn[1:0] in Reg0xCA is set to

2hex, Four Channel ITU-R BT.656(D1) Time-multiplexed Format is output on VDn[7:0] pin.

EXTRA SYNC OUTPUT

The additional timing information such as syncs and field flag are also supported through the MPP pins. The video

output timing is illustrated in Fig13 and Fig14 TW2864 HS/VS/FLD output function is compatible to TW9907 Video

decoder HSYNC/VSYNC/FIELD output function. Start of VS timing is controlled by VSHT register(V timing) and OVSDLY

OFDLY register(V timing).Start of HS timing is controlled by HSBEGIN register and End of HS timing is controlled by

HSEND register.

TW2864D Datasheet(PDF) 27 Page - Renesas Technology Corp