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TW2864D Datasheet(PDF) 62 Page - Renesas Technology Corp |
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TW2864D Datasheet(HTML) 62 Page - Renesas Technology Corp |
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62 / 110 page  TW2864 FN7745 Rev. 0.00 Page 62 of 110 September 28, 2012 0XA4(CH1)/0XA5(CH2)/0XA6(CH3)/0XA7(CH4) – ID DETECTION CONTROL BIT FUNCTION R/W DESCRIPTION RESET 7-6 IDX R/W These two bits indicate which of the four lower 6-bit registers is currently being controlled. The write sequence is a two steps process unless the same register is written. A write of {ID,000000} selects one of the four registers to be written. A subsequent write will actually write into the register. 0 5-0 NSEN / SSEN / PSEN / WKTH R/W IDX = 0 controls the NTSC color carrier detection sensitivity (NSEN). IDX = 1 controls the SECAM ID detection sensitivity (SSEN). IDX = 2 controls the PAL ID detection sensitivity (PSEN). IDX = 3 controls the weak signal detection sensitivity (WKTH). 1A / 20 / 1C / 2A 0XC4(CH1)/0XC5(CH2)/0XC6(CH3)/0XC7(CH4) – H MONITOR BIT FUNCTION R/W DESCRIPTION RESET 7-0 HFREF R Horizontal line frequency indicator (Test purpose only) X 0X80 – SOFTWARE RESET CONTROL REGISTER BIT FUNCTION R/W DESCRIPTION RESET 7-6 Reserved R Reserved 00b 5 AUDIORST W A 1 written to this bit resets the Audio portion to its default state but all register content remains unchanged. This bit is self-resetting. 0 4 VOUTRST W A 1 written to this bit resets Video data mux output logic to its default state but all register content remain unchanged. This bit is self-resetting. 0 3 VDEC4RST W A 1 written to this bit resets the Video4 Decoder portion to its default state but all register content remain unchanged. This bit is self-resetting. 0 2 VDEC3RST W A 1 written to this bit resets the Video3 Decoder portion to its default state but all register content remain unchanged. This bit is self-resetting. 0 1 VDEC2RST W A 1 written to this bit resets the Video2 Decoder portion to its default state but all register content remain unchanged. This bit is self-resetting. 0 0 VDEC1RST W A 1 written to this bit resets the Video1 Decoder portion to its default state but all register content remain unchanged. This bit is self-resetting. 0 0X81 – ANALOG CONTROL REGISTER BIT FUNCTION R/W DESCRIPTION RESET 7 Reserved R Reserved 0 6 IREF R/W 0 = Internal current reference 1. 1 = Internal current reference increase 30%. 0 5 VREF R/W 0 = Internal voltage reference. 1 = Internal voltage reference shut down. 0 4 Reserved R/W 0 = Normal operation(must be 0), 1 = AIGAINTEST 0 3 CLKPDN R/W 0 = Normal clock operation. 1 = All 4Ch Video Decoder System clock in power down mode, but the MPU INTERFACE module and output clocks (CLKP and CLKN) are still active. 0 |
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