TW2864D datasheet(31/110 Pages) RENESAS

31 / 110 page

TW2864

FN7745 Rev. 0.00

Page 31 of 110

September 28, 2012

ASYNR pin can be input or output by external Audio clock master in slave mode. ASYNR signal should change per fs

audio sample rate in both master and slave mode.

AUDIO DETECTION

The TW2864 has an audio detector for individual 4 channels. There are 2 kinds of audio detection method defined by

the ADET_MTH. One is the detection of absolute amplitude and the other is of differential amplitude. For both

detection methods, the accumulating period is defined by the ADET_FILT register and the detecting threshold value is

defined by the ADET_TH1 ~ ADET_TH4 registers. The status for audio detection is read by the STATE_AVDET register

and it also makes the interrupt request through the IRQ pin with the combination of the status for video loss

detection.

MULTI-CHIP OPERATION

TW2864 can output 16 channel audio data on ACLKR/ASYNR/ADATR output simultaneously. Therefore, up to 4 chips

should be connected on most Multi-Chip application cases. SMD register selects Audio cascade serial interface mode.

If SMD register is set to 1, IRQ pin is audio cascade serial output and ADATP pin is audio cascade serial input.This is

IRQ cascade mode. If SMD register is set to 2, ALINKI pin is audio cascade serial input and ALINKO pin is audio

cascade serial output mode. It’s ALINK cascade mode. If SMD register is set to 0, ALINKO pin is input.ALINKO pin

default is also input.

Each stage chip can accept 4 analog audio signals so that four cascaded chips through the ADATP and IRQ pin will be

16-channel audio controller. The first stage chip provides 16ch digital serial audio data for record. Even though the

first stage chip has only 1 digital serial audio data pin ADATR for record, the TW2864 can generate 16 channel data

simultaneously using multi-channel method. Also, each stage chip can support 4 channel record outputs that are

corresponding with analog audio inputs. This first stage chip can also output 16 channel mixing audio data by the

digital serial audio data and analog audio signal. The last stage chip accepts the digital serial audio data for playback.

The digital playback data can be converted to analog signal by Digital-to-Analog Converter in the last stage chip.

In Multi-Chip Audio operation mode,one same Oscillator clock source(108MHz or 54MHz) need to be connected to all

CLKI pins.One 27MHz clock source can be connected if needed,too.

Several Master/Slave mode configurations are available.The Fig16-1/Fig16-2/Fig16-3/Fig16-4/Fig16-5/Fig16-6

show all possible

systems of 16 channel audio connection using 4

chips

with

Clock Master

mode(ACLKRMASTER=1).Fig16-7 is the most recommended and demanded system with Clock Master

mode(ACLKRMASTER=1).Fig16-8

the

most

recommended

system with

Clock

Slave

Sync

Master

mode(ACLKRMASTER=0,ASYNROEN=0).Fig16-9 is the most recommended system with Clock Slave Sync Slave

mode(ACLKRMASTER=0,ASYNROEN=1) .

If All Clock Sync is required in system,one same RSTB reset# signal needs to be connected to all RSTB pins.If ALINK

cascade mode,in this All Clock Sync system,all ACLKR pins and all ACLKP pins should be connected. Also,all ASYNR

pins and all ASYNP pins should be connected.If IRQ cascade mode, in this All Clock Sync system,all ACLKR pins and

LastStage ACLKP pin should be connected.Also,all ASYNR pins and LastStage ASYNP pin should be connected.

In following each Fig,Mix1-16-Pb1-Pb4 means Mix output of AIN1-16 and Playback1-4.AIN1-16 means one selected

Audio output in AIN1-16.Pb1-Pb4 means one selected Audio output in Playback1-4.Mix1-16-Pb4 means Mix output of

TW2864D Datasheet(PDF) 31 Page - Renesas Technology Corp

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