TW2864D datasheet(65/110 Pages) RENESAS

65 / 110 page

TW2864

FN7745 Rev. 0.00

Page 65 of 110

September 28, 2012

0X8B– CLAMP LEVEL

BIT

FUNCTION

R/W

DESCRIPTION

RESET

CLMPLD

R/W

0 = Clamping level is set by CLMPL.

1 = Clamping level preset at 60d.

6-0

CLMPL

R/W

These bits determine the clamping level of the Y channel.

0X8C– SYNC AMPLITUDE

BIT

FUNCTION

R/W

DESCRIPTION

RESET

SYNCTD

R/W

0 = Reference sync amplitude is set by SYNCT.

1 = Reference sync amplitude is preset to 38h.

6-0

SYNCT

R/W

These bits determine the standard sync pulse amplitude for AGC

reference.

0X8D – SYNC MISS COUNT REGISTER

BIT

FUNCTION

R/W

DESCRIPTION

RESET

7-4

MISSCNT

R/W

These bits set the threshold for horizontal sync miss count threshold.

3-0

HSWIN

R/W

These bits determine the VCR mode detection threshold.

0X8E – CLAMP POSITION REGISTER

BIT

FUNCTION

R/W

DESCRIPTION

RESET

7-0

PCLAMP

R/W

These bits set the clamping position from the internal PLL sync edge

0X8F – VERTICAL CONTROL I

BIT

FUNCTION

R/W

DESCRIPTION

RESET

7-6

VLCKI

R/W

Vertical lock in time.

0 = fastest

3 = slowest.

5-4

VLCKO

R/W

Vertical lock out time.

0 = fastest

3 = slowest.

VMODE

R/W

This bit controls the vertical detection window.

1 = search mode.

0 = vertical count down mode.

DETV

R/W

1 = recommended for special application only.

0 = Normal Vsync logic

AFLD

R/W

Auto field generation control

0 = Off

1 = On

VINT

R/W

Vertical integration time control.

1 = short

0 = normal

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