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TW2864D Datasheet(PDF) 46 Page - Renesas Technology Corp |
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TW2864D Datasheet(HTML) 46 Page - Renesas Technology Corp |
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46 / 110 page  TW2864 FN7745 Rev. 0.00 Page 46 of 110 September 28, 2012 AUDIO CLOCK SLAVE MODE DATA INPUT TIMING ADATP data input has two kind of delay timings according to ACLKP/ASYNP input timing. ADATP data needs to be input from next ACLKP falling edge after ASYNP signal changes. ASYNP is ACLKP falling edge triggered input MSB LSB MSB LSB MSB 1/fs ASYNP ACLKP ADATP Data 1 Data 2 FIGURE 31. ACLKMASTER=0,RM_SYNC=0,PB_MASTER=0 MSB LSB MSB LSB MSB 1/fs ASYNP ACLKP ADATP Data 1 Data 2 FIGURE 32. ACLKMASTER=0,RM_SYNC=1,PB_MASTER=0 ASYNP is ACLKP rising edge triggered input MSB LSB MSB LSB MSB 1/fs ASYNP ACLKP ADATP Data 1 Data 2 FIGURE 33. ACLKMASTER=0,RM_SYNC=0,PB_MASTER=0 |
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