TW2864D datasheet(80/110 Pages) RENESAS

80 / 110 page

TW2864

FN7745 Rev. 0.00

Page 80 of 110

September 28, 2012

Index

Serial Mode Control

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

0xCF

SMD

VRSTSEL

FIRSTCNUM

SMD

Set up cascade Audio Serial mode.

When SMD=2hex or 3hex,ALINKO pin is output pin.When SMD=0hex or 1hex,ALINKO pin is

input. TW2815 chip can be replaced with 54MHz clock-in TW2864B/TW2864D chip under

SMD=0hex/1hex setting.

00 No Serial mode. ALINKO pin is test input mode.(default)

01 TW2815 Serial mode. IRQ pin is Serial out pin. ADATP pin is Serial

input pin.

10 ALINKO pin is Serial out pin. ALINKI pin is Serial input pin.

VRSTSEL

Select VRST(V reset) signal on ACKG (Audio Clock Generator) refin input .

Ch1 VRST (default)

Ch2 VRST

Ch3 VRST

Ch4 VRST

FIRSTCNUM

This function is only effective in SMD=01h mode.

Set up 0h on Last(Bottom)Stage chip.

If 4 chip cascade mode,set up 3h on FirstStage/SecondStage/ThirdStage chips and 0h on

LastStage chip.

If 3 chip cascade mode,set up 2h on FirstStage/SecondStage and 0h on ThirdStage chip.

If 2 chip cascade mode,set up 1h on FirstStage chip and 0h on SecondStage chip.

If single chip application mode, this register doesn’t need to be set up.

(default)

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