TW2864D datasheet(48/110 Pages) RENESAS

48 / 110 page

TW2864

FN7745 Rev. 0.00

Page 48 of 110

September 28, 2012

AUDIO CLOCK GENERATION

TW2864 has built-in field locked audio clock generator for use in video capture applications. The circuitry will

generate the same pre-defined number of audio sample clocks per field to ensure synchronous playback of video and

audio after digital recording or compression. The audio clock is digitally synthesized from the crystal clock input with

reference to the incoming video. The master audio clock frequency is programmable through ACKN and ACKI register

based on the following two equations.

ACKN

round

(

AMCLK

field

gives

the

Audio

master

Clock

Per

Field.

ACKI = round ( F AMCLK / F 27MHz * 2^23 ),it gives the Audio master Clock Nominal increment.

The following table provides setting examples of some commonly used audio frequencies, assuming a Video Decoder

system clock frequency of 27MHz.

AMCLK(MHZ)

FIELD[HZ]

ACKN [DEC]

ACKN [HEX]

ACKI [DEC]

ACKI [HEX]

256 x 48 KHz

12.288

245760

3-C0-00

3817749

3A-41-15

12.288

59.94

205005

3-20-CD

3817749

3A-41-15

256 x 44.1KHz

11.2896

225792

3-72-00

3507556

35-85-65

11.2896

59.94

188348

2-DF-BC

3507556

35-85-65

256 x 32 KHz

8.192

163840

2-80-00

2545166

26-D6-0E

8.192

59.94

136670

2-15-DE

2545166

26-D6-0E

256 x 16 KHz

4.096

81920

1-40-00

1272583

13-6B-07

4.096

59.94

68335

1-0A-EF

1272583

13-6B-07

256 x 8 KHz

2.048

40960

A0-00

636291

9-B5-83

2.048

59.94

34168

85-78

636291

9-B5-83

If ACLKRMASTER register bit is set to 1, this AMCLK(256xfs) is used as audio system clock inside TW2864 chip.

[REV_ID>=1 TW2864 only]

If Slave Playback-in lock mode is required, ACKN=00100hex and PBREFEN=1 needs to be set up. The number of

AMCLK clock per one ASYNP input cycle is locked (fixed) to 256 in this mode.

The frequency equation is “AMCLK(Freq) = 256 x ASYNP(Freq)”.

TW2864D Datasheet(PDF) 48 Page - Renesas Technology Corp

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