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IMX93CEC Datasheet(PDF) 103 Page - NXP Semiconductors |
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IMX93CEC Datasheet(HTML) 103 Page - NXP Semiconductors |
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103 / 123 page  Table 105. 9 x 9 mm functional contact assignment Ball name 9 x 9 ball Power group Ball Types Default setting Default modes Default function Status while reset is asserted ADC_IN0 B8 VDD_ANA0_1P8 ANALOG — — Input without PU[1] / PD[2] ADC_IN1 A8 VDD_ANA0_1P8 ANALOG — — Input without PU / PD CCM_CLKO1 T4 NVCC_WAKEUP GPIO Alt0 CCMSRCGPCMIX.CLK01 Output low CLKIN1 A6 VDD_ANA_1P8 ANALOG — — Input without PU / PD CLKIN2 B6 VDD_ANA_1P8 ANALOG — — Input without PU / PD DAP_TCLK_SWCLK U3 NVCC_WAKEUP GPIO Alt0 DAP.TCLK_SWCLK Input with PD DAP_TDI P8 NVCC_WAKEUP GPIO Alt0 DAP.TDI Input with PU DAP_TDO_TRACESW O T3 NVCC_WAKEUP GPIO Alt0 DAP.TDO_TRACESWO Input without PU/PD DAP_TMS_SWDIO P6 NVCC_WAKEUP GPIO Alt0 DAP.TMS_SWDIO Input with PU DRAM_CA0_A F1 VDDQ_DDR DDR — — — DRAM_CA1_A E2 VDDQ_DDR DDR — — — DRAM_CA2_A D2 VDDQ_DDR DDR — — — DRAM_CA3_A C1 VDDQ_DDR DDR — — — DRAM_CA4_A B2 VDDQ_DDR DDR — — — DRAM_CA5_A A2 VDDQ_DDR DDR — — — DRAM_CK_C_A B1 VDDQ_DDR DDR — — — DRAM_CK_T_A C2 VDDQ_DDR DDR — — — DRAM_CKE0_A G1 VDDQ_DDR DDR — — — DRAM_CKE1_A F2 VDDQ_DDR DDR — — — DRAM_CS0_A D1 VDDQ_DDR DDR — — — DRAM_CS1_A E1 VDDQ_DDR DDR — — — Table continues on the next page... NXP Semiconductors IMX93CEC i.MX 93 Applications Processors Data Sheet for Commercial Products IMX93CEC All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 7 — 12 February 2026 Document feedback 103 / 123 |
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