XC2000 datasheet(113/647 Pages) INFINEON

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XC2000 Derivatives

System Units (Vol. 1 of 2)

Memory Organization

Preliminary

User’s Manual

3-51

V1.0, 2007-06

MemoryX2K, V1.1

instructions on the predicted branch in advance. In case of a misprediction this interface

can abort outstanding requests and continues fetching on the correct branch. As the

CPU can consume up to one 32-bit instruction per clock cycle the performance of this

interface determines the CPU performance.

The data bus is controlled by the data management unit “DMU” of the CPU. It reads data

in words of 16 bits. Write accesses address as well 16-bit words but additional byte

enables allow changing single bytes.

Because of the CPU’s “von Neumann” architecture data and instructions (and “special

function registers” to complete the list) share a common address range. When

instructions are used as data (e.g. when copying code from an IO interface to the

PSRAM) they are accessed via the data bus. The pipelined behavior of the CPU can

cause that code fetches and data accesses are requested simultaneously. The IMB

takes care that accesses can perform concurrently if they address different memories or

flash modules.

Additional connections of the IMB to central system control units exist. These are not

shown in the block diagram.

XC2000 Datasheet(PDF) 113 Page - Infineon Technologies AG