SH7616 datasheet(107/935 Pages) RENESAS

107 / 935 page

Section 2 CPU

Rev. 2.00 Mar 09, 2006 page 81 of 906

REJ09B0292-0200

Instruction

Instruction Code

Operation

Cycles

T Bit

SUB

Rm,Rn

0011nnnnmmmm1000

Rn–Rm

→ Rn

—

SUBC

Rm,Rn

0011nnnnmmmm1010

Rn–Rm–T

→ Rn,

Borrow

→ T

Borrow

SUBV

Rm,Rn

0011nnnnmmmm1011

Rn–Rm

→ Rn,

Underflow

→ T

Underflow

Note: * The normal number of execution cycles. The number in parentheses is the number of

execution cycles in the case of contention with preceding or following instructions.

Table 2.22 Logic Operation Instructions

Instruction

Instruction Code

Operation

Cycles

T Bit

AND

Rm,Rn

0010nnnnmmmm1001

Rn & Rm

→ Rn

—

AND

#imm,R0

11001001iiiiiiii

R0 & imm

→ R0

—

AND.B

#imm,@(R0,GBR)

11001101iiiiiiii

(R0 + GBR) & imm

→

(R0 + GBR)

3—

NOT

Rm,Rn

0110nnnnmmmm0111

~Rm

→ Rn

—

Rm,Rn

0010nnnnmmmm1011

Rn | Rm

→ Rn

—

#imm,R0

11001011iiiiiiii

R0 | imm

→ R0

—

OR.B

#imm,@(R0,GBR)

11001111iiiiiiii

(R0 + GBR) | imm

→

(R0 + GBR)

3—

TAS.B

@Rn

0100nnnn00011011

If (Rn) is 0, 1

→ T,

→ MSB of (Rn)

4Test

result

TST

Rm,Rn

0010nnnnmmmm1000

Rn & Rm, if the result is

0, 1

→ T

1Test

result

TST

#imm,R0

11001000iiiiiiii

R0 & imm, if the result is

0, 1

→ T

1Test

result

TST.B

#imm,@(R0,GBR)

11001100iiiiiiii

(R0 + GBR) & imm, if the

result is 0, 1

→ T

3Test

result

XOR

Rm,Rn

0010nnnnmmmm1010

Rn ^ Rm

→ Rn

—

XOR

#imm,R0

11001010iiiiiiii

R0 ^ imm

→ R0

—

XOR.B

#imm,@(R0,GBR)

11001110iiiiiiii

(R0 + GBR) ^ imm

→

(R0 + GBR)

3—

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