SH7616 datasheet(201/935 Pages) RENESAS

201 / 935 page

Section 5 Interrupt Controller (INTC)

Rev. 2.00 Mar 09, 2006 page 175 of 906

REJ09B0292-0200

5.3.18

Vector Number Setting Register L (VCRL)

Vector number setting register L (VCRL) is a 16-bit read/write register that sets the serial

communication interface with FIFO 1 (SCIF1) receive-error interrupt and receive-data-full/data-

ready interrupt vector numbers (0–127).

VCRL is initialized to H'0000 by a reset. It is not initialized in standby mode.

Bit:

—

SER1V6 SER1V5 SER1V4 SER1V3 SER1V2 SER1V1 SER1V0

Initial value:

00000000

R/W:

R/W

Bit:

76543210

—

SRX1V6 SRX1V5 SRX1V4 SRX1V3 SRX1V2 SRX1V1 SRX1V0

Initial value:

00000000

R/W:

R/W

Bits 15 and 7—Reserved: These bits are always read as 0. The write value should always be 0.

Bits 14 to 8—Serial Communication Interface with FIFO 1 (SCIF1) Receive-Error Interrupt

Vector Number 6 to 0 (SER1V6–SER1V0): These bits set the vector number for the serial

communication interface with FIFO 1 (SCIF1) receive-error interrupt. There are seven bits, so the

value can be set between 0 and 127.

Bits 6 to 0—Serial Communication Interface with FIFO 1 (SCIF1) Receive-Data-Full/Data-Ready

Interrupt Vector Number 6 to 0 (SRX1V6–SRX1V0): These bits set the vector number for the

serial communication interface with FIFO 1 (SCIF1) receive-data-full/data-ready interrupt. There

are seven bits, so the value can be set between 0 and 127.

SH7616 Datasheet(PDF) 201 Page - Renesas Technology Corp