SH7727 datasheet(152/1109 Pages) RENESAS

152 / 1109 page

Section 2 CPU

Rev. 5.00 Dec 12, 2005 page 80 of 1034

REJ09B0254-0500

2.6.2

Added CPU System Control Instructions

The new instructions in this class are treated as part of the CPU core functions, and therefore all

the added instructions have a 16-bit code length. All the additional instructions belong to the

system control instruction group. Table 2.26 summarizes the added system instructions. New

control registers—RS, RE, and MOD—have been added to the CPU core to support loop control

and modulo addressing functions, and LDC and STS type instructions have been provided for

these registers.

The DSP engine’s DSR, A0, X0, X1, Y0, and Y1 registers are treated as system registers such as

MACH and MACL, and therefore STS and LDS instructions are supported for these registers. As

digital signal processing operations usually employ a multi-level nested-loop structure, DSP

performance can be improved by means of a zero-overhead loop control function. SETRC type

instructions are provided to set the repeat count in the RC field in SR[27:16]. When an immediate

operand type SETRC instruction is executed, the 8-bit immediate operand data is set in SR[23:16],

and 0 is set in the remaining bits, SR[27:24]. When a register operand type SETRC instruction is

executed, Rn[11:0] is set in SR[27:16]. The start address and end address of the repeat loop are set

in the RS register and RE register. There are two ways of setting the addresses: by using an LDC

type instruction, or by using the LDRS and LDRE instructions.

SH7727 Datasheet(PDF) 152 Page - Renesas Technology Corp