SH7727 datasheet(151/1109 Pages) RENESAS

151 / 1109 page

Section 2 CPU

Rev. 5.00 Dec 12, 2005 page 79 of 1034

REJ09B0254-0500

2.6

DSP Extended-Function Instructions

2.6.1

Introduction

The newly added instructions are classified into the following three groups:

1. Additional system control instructions for the CPU unit

2. DSP unit memory-register single and double data transfer

3. DSP unit parallel processing

Group 1 instructions are provided to support loop control and data transfer between CPU core

registers or memory and new control registers added to the CPU core. DSP operations employ a

multi-level nested-loop structure. With a single-level loop, use of the decrement and test, DTRn,

and conditional delayed branch BF/S instructions supported by the SH-3 is adequate. However,

with nested loops, DSP performance can be improved by means of a zero-overhead loop control

function.

The RS, RE, and MOD registers have been added to support loop control and modulo addressing

functions. Instructions are supported for data transfer between these new control registers and

general registers or memory. In addition, the LDRS and LDRE address calculation registers have

been added to reduce the code size for the initial settings for zero-overhead loop control.

An independent control register, DSR, is provided for the DSP engine. This register is treated as a

system register such as MACL and MACH. The A0, X0, X1, Y0, and Y1 registers are treated as

system registers from the CPU side, and LDS/STS instructions are supported for the same

purpose. Table 2.26 shows the instruction code map for the new system control instructions for the

CPU core.

Group 2 instructions are provided to reduce DSP operation program code size. Data transfer

instructions that perform no data processing are frequently executed by the DSP engine. In this

case, a 32-bit instruction code is unnecessarily long, and wastes space in the program memory

area. All instructions in this class have a 16-bit code length, the same as conventional SH core

instructions. Single data transfer instructions have greater flexibility in terms of operands than the

double data transfer instruction or parallel instruction class.

Group 3 instructions are provided for fast execution of digital signal processing operations using

the DSP unit. These instructions have a 32-bit instruction code, so that a maximum of four

instructions—an ALU operation, multiplication, and two data transfer instructions—can be

executed in parallel.

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