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SH7727 Datasheet(PDF) 157 Page - Renesas Technology Corp |
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SH7727 Datasheet(HTML) 157 Page - Renesas Technology Corp |
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157 / 1109 page  Section 2 CPU Rev. 5.00 Dec 12, 2005 page 85 of 1034 REJ09B0254-0500 The correspondence between DSP data transfer operands and registers is shown in table 2.29. CPU core registers are used as a pointer address that indicates a memory address. Table 2.29 Correspondence between DSP Data Transfer Operands and Registers Register Ax Ix Dx Ay Iy Dy Da As Ds R0 CPU register R1 R2 (As2) Yes R3 (As3) Yes R4 (Ax0) Yes Yes R5 (Ax1) Yes Yes R6 (Ay0) Yes R7 (Ay1) Yes R8 (Ix) Yes R9 (Iy) Yes A0 Yes Yes DSP register A1 Yes Yes M0 Yes M1 Yes X0 Yes Yes X1 Yes Yes Y0 Yes Yes Y1 Yes Yes A0G Yes A1G Yes 2.6.4 DSP Operation Instruction Set DSP operation instructions are instructions for digital signal processing performed by the DSP unit. These instructions have a 32-bit instruction code, and multiple instructions can be executed in parallel. The instruction code is divided into an A field and B field; a parallel data transfer instruction is specified in the A field, and a single or double data operation instruction in the B field. Instructions can be specified independently, and are also executed independently. The parallel data transfer instruction specified in the A field is exactly the same as a double data transfer instruction. The function of the A field—that is, the data transfer instruction field—is |
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