SH7727 datasheet(170/1109 Pages) RENESAS

170 / 1109 page

Section 3 Memory Management Unit (MMU)

Rev. 5.00 Dec 12, 2005 page 98 of 1034

REJ09B0254-0500

When address translation from virtual memory to physical memory is performed using the MMU,

it may occur that the relevant translation information is not recorded in the MMU, with the result

that one process may inadvertently access the virtual memory allocated to another process. In this

case, the MMU will generate an exception, change the physical memory mapping, and record the

new address translation information.

Although the functions of the MMU could also be implemented by software alone, the need for

translation to be performed by software each time a process accesses physical memory would

result in poor efficiency. For this reason, a buffer for address translation (translation look-aside

buffer: TLB) is provided in hardware to hold frequently used address translation information. The

TLB can be described as a cache for storing address translation information. Unlike cache

memory, however, if address translation fails, that is, if an exception is generated, switching of

address translation information is normally performed by software. This makes it possible for

memory management to be performed flexibly by software.

The MMU has two methods of mapping from virtual memory to physical memory: a paging

method using fixed-length address translation, and a segment method using variable-length

address translation. With the paging method, the unit of translation is a fixed-size address space

(usually of 1 to 64 kbytes) called a page.

In the following text, the SH7727 address space in virtual memory is referred to as logical address

space, and address space in physical memory as physical memory space.

SH7727 Datasheet(PDF) 170 Page - Renesas Technology Corp