SH7727 datasheet(173/1109 Pages) RENESAS

173 / 1109 page

Section 3 Memory Management Unit (MMU)

Rev. 5.00 Dec 12, 2005 page 101 of 1034

REJ09B0254-0500

H'80000000

H'A0000000

H'C0000000

H'E0000000

H'FFFFFFFF

2-Gbyte virtual space,

cacheable

(write-back/write-through)

2-Gbyte virtual space,

cacheable

(write-back/write-through)

Address error

H'00000000

H'80000000

H'FFFFFFFF

Area P0

Area P1

Area P2

Area P3

Area P4

Area U0

Area Uxy

(present

only when

SR.DSP=1)

Privileged mode

User mode

0.5-Gbyte fixed physical

space, cacheable

(write-back/write-through)

0.5-Gbyte fixed

physical space,

non-cacheable

0.5-Gbyte virtual space,

cacheable

(write-back/write-through)

0.5-Gbyte control space,

non-cacheable

Figure 3.2 Logical Address Space Mapping

Physical Address Space: The SH7727 supports a 32-bit physical address space, but the upper 3

bits are actually ignored and treated as a shadow. See section 12, Bus State Controller (BSC), for

details.

Address Translation: When the MMU is enabled, the logical address space is divided into units

called pages. Physical addresses are translated in page units. Address translation tables in external

memory hold information such as the physical address that corresponds to the logical address and

memory protection codes. When an access to an area other than P4 occurs, if the accessed logical

address belongs to area P1 or P2 there is no TLB access and the physical address is uniquely

defined. If it belongs to area P0, P3 or U0, the TLB is searched by logical address and, if that

logical address is registered in the TLB, the access hits the TLB. The corresponding physical

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