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SH7727 Datasheet(PDF) 175 Page - Renesas Technology Corp

Part # SH7727
Description  Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series
PDF  1109 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7727 Datasheet(HTML) 175 Page - Renesas Technology Corp

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Section 3 Memory Management Unit (MMU)
Rev. 5.00 Dec 12, 2005 page 103 of 1034
REJ09B0254-0500
3.1.4
Register Configuration
Table 3.1 shows the configuration of the MMU control registers.
Table 3.1
Register Configuration
Name
Abbreviation
R/W Size
Initial Value*
1
Address
Page table entry register high PTEH
R/W Longword
Undefined
H'FFFFFFF0
Page table entry register low
PTEL
R/W Longword
Undefined
H'FFFFFFF4
Translation table base
register
TTB
R/W Longword
Undefined
H'FFFFFFF8
TLB exception address
register
TEA
R/W Longword
Undefined
H'FFFFFFFC
MMU control register
MMUCR
R/W Longword
*2
H'FFFFFFE0
Notes: 1. Initialized by a power-on reset or manual reset.
2. SV bit = undefined
Other bits = 0
3.2
Register Description
There are five registers for MMU processing. These are all peripheral module registers, so they are
located in address space area P4 and can only be accessed from privileged mode by specifying the
address. These registers consist of:
1. The page table entry register high (PTEH) register residing at address H'FFFFFFF0, which
consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the logical
address at which the exception is generated in case of an MMU exception or address error
exception. When the page size is 4 kbytes, the VPN is the upper 20 bits of the logical address,
but in this case the upper 22 bits of the logical address are set. The VPN can also be modified
by software. As the ASID, software sets the number of the currently executing process. The
VPN and ASID are recorded in the TLB by the LDTLB instruction.
2. The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to
store the physical page number and page management information to be recorded in the TLB
by the LDTLB instruction. The contents of this register are only modified in response to a
software command.
3. The translation table base register (TTB) residing at address H'FFFFFFF8, which points to the
base address of the current page table. The software does not set any value in TTB
automatically. TTB is available to software for general purposes.



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