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HD6433713 Datasheet(PDF) 178 Page - Renesas Technology Corp |
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HD6433713 Datasheet(HTML) 178 Page - Renesas Technology Corp |
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178 / 324 page  8.7 Interrupts Timer A to E interrupts are requested when a timer overflows or underflows. Each timer is assigned its own vector address. The priority of interrupts is in the order of timer A (high) to timer E (low). Further details are given in 3.2.2, Interrupts, table 3-2, Interrupt Sources. When timers A to E overflow, the corresponding bit IRRTA to IRRTE in interrupt request register 2 (IRR2) is set to 1. These interrupt flags are not cleared even if the interrupt is accepted. They must be cleared to 0 by software in the interrupt handler routine. Interrupts may be enabled or disabled independently for each timer by means of bits IENTA to IENTE in interrupt enable register 2 (IENR2). For further details see 3.2.3, Interrupt Control Registers. 8.8 Application Notes Even when the EVENT bit in port mode register 1 (PMR1) designates the P16 usage of pin P16/EVENT, reading the P16 pin may cause timer D to increment. When using timer D, be sure to clear timer counter D (TCD) by means of the CLR bit in timer mode register D (TMD). 167 |
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