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HD6433713 Datasheet(PDF) 258 Page - Renesas Technology Corp |
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HD6433713 Datasheet(HTML) 258 Page - Renesas Technology Corp |
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258 / 324 page  Table 14-9 Control Signal Timing (cont) Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC – 40 to VCC, VSS = 0.0 V, Ta = –20 to +75°C Rating Item Symbol Test Conditions Min Typ Max Unit RES pin pulse tREL RES VCC = 2.7 to 5.5 V 10 — — φ Figure width (low) 14-2 IRQ pin pulse tIH IRQ0, IRQ1 VCC = 2.7 to 5.5 V 2 — — φ Figure width (high) IRQ4, IRQ5 φ SUB 14-3 IRQ pin pulse tIL IRQ0, IRQ1 VCC = 2.7 to 5.5 V 2 — — φ width (low) IRQ4, IRQ5 φ SUB EVENT pin tEVH EVENT VCC = 2.7 to 5.5 V 2 — — φ Figure pulse width (high) 14-4 EVENT pin tEVL EVENT VCC = 2.7 to 5.5 V 2 — — φ pulse width (low) UD pin minimum tUDH UD VCC = 2.7 to 5.5 V 2 — — φ Figure high/low width tUDL 14-5 Table 14-10 Serial Interface Timing Conditions: Unless otherwise indicated, VCC = 4.0 to 5.5 V, Vdisp = VCC – 40 to VCC, VSS = 0.0 V, Ta = –20 to +75°C Rating Item Symbol Test Conditions Min Typ Max Unit Output serial tscyc SCK1, VCC = 2.7 to 5.5 V 2 — — φ Figure clock cycle timing SCK2 14-6 Output serial tSCKH SCK1,VCC = 2.7 to 5.5 V 0.4 — — tscyc clock pulse width SCK2 (high) Output serial tSCKL SCK1,VCC = 2.7 to 5.5 V 0.4 — — tscyc clock pulse SCK2 width (low) tSCKr —— 60 ns VCC = 2.7 to 5.5 V — — 80 tSCKf —— 60 ns VCC = 2.7 to 5.5 V — — 80 Input serial tscyc VCC = 2.7 to 5.5 V 1 — — φ clock cycle timing Input serial tSCKH VCC = 2.7 to 5.5 V 0.4 — — tscyc clock pulse width (high) Applicable Pins Reference Diagram Applicable Pins Reference Diagram Output serial clock rise time Output serial clock fall time SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 SCK1, SCK2 247 |
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